US5847576A
Expired / Lapsed
US
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Low power, variable logic threshold voltage, logic gates
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-11-07
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Granted: 1998-12-08
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Expires: 2016-11-07
Abstract
Abstract A logic gate arrangement having a master gate or section for controlling the logic threshold voltage of slave gates responsive to the master. Both the master and slave gates have two opposite conductivity type transistors disposed in combination with a logic function circuit. The transistors have a common gate connection to a control input. Varying the voltage on the control input varies the logic threshold voltage of the gate. The logic function in the master gate is typically an inverter, with input and output connected together and driving the control inputs of the slave gates. The logic function of the slave gates may be a variety of different logic functions. The logic threshold voltage of the slave gates is substantially the same as a voltage applied to the control input of the master gate.
Inventors
- 👤 Angelo Rocco Mastrocola
- 👤 Scott Wayne McLellan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:57
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0021; H03K19/0027; H03K19/0008; H03K19/0013
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
306 words
An integrated circuit comprising a logic gate and a master gate, the logic gate comprising: at least one transistor of a first conductivity type and at least one transistor of a second conductivity type in combination with additional first and second conductivity type transistors to provide a desired logic function; a transistor of the first conductivity type, responsive to a control signal, with outputs in series with the at least one transistor of the first type; a transistor of the second conductivity type, responsive to the control signal, with outputs in series with the at least one transistor of the second conductivity type; and a transistor, responsive to the control signal, in series with one of the additional first or second conductivity type transistors and of the same conductivity type; wherein the logic gate has a logic threshold voltage that varies in response to the control signal; a master gate, generating the control signal at an output, comprising: first, second, third and fourth transistors, each having an input terminal and two outputs, the outputs being serially connected between a first power supply rail and a second power supply rail, the connection between a middle two of the transistors being the output; wherein the master gate includes additional first and second conductivity type transistors to implement the same logic function as the logic gate, the input terminal of the second and third transistors being connected together and coupled to the output, the input terminal of the first and fourth transistors being connected together, the first and second transistors are of the first conductivity type and the third and fourth transistors are of the second conductivity type, and wherein the logic threshold voltage of the logic gate is substantially equal to a voltage applied to the input terminals of the first and fourth terminals of the master gate.
Claim 2
Dependent Claim
306 words
An integrated circuit comprising a logic gate and a master gate, the logic gate comprising: at least one transistor of a first conductivity type and at least one transistor of a second conductivity type in combination with additional first and second conductivity type transistors to provide a desired logic function; a transistor of the first conductivity type, responsive to a control signal, with outputs in series with the at least one transistor of the first type; a transistor of the second conductivity type, responsive to the control signal, with outputs in series with the at least one transistor of the second conductivity type; and a transistor, responsive to the control signal, in series with one of the additional first or second conductivity type transistors and of the same conductivity type; wherein the logic gate has a logic threshold voltage that varies in response to the control signal; a master gate, generating the control signal at an output, comprising: first, second, third and fourth transistors, each having an input terminal and two outputs, the outputs being serially connected between a first power supply rail and a second power supply rail, the connection between a middle two of the transistors being the output; wherein the master gate includes additional first and second conductivity type transistors to implement the same logic function as the logic gate, the input terminal of the second and third transistors being connected together and coupled to the output, the input terminal of the first and fourth transistors being connected together, the first and second transistors are of the first conductivity type and the third and fourth transistors are of the second conductivity type, and wherein the logic threshold voltage of the logic gate is substantially equal to a voltage applied to the input terminals of the first and fourth terminals of the master gate.
Claim 3
Dependent Claim
25 words
The master gate as recited in claim 1, further characterized the first and fourth transistors being connected to the first and second power rails, respectively.
Claim 4
Dependent Claim
25 words
The master gate as recited in claim 1, further characterized the first and third transistors being connected to the first and second power rails, respectively.
Claim 5
Dependent Claim
25 words
The master gate as recited in claim 1, further characterized the second and third transistors being connected to the first and second power rails, respectively.
Claim 6
Dependent Claim
16 words
The logic gate as recited in claim 1, wherein the logic function is a NAND function.
Claim 7
Dependent Claim
16 words
The logic gate as recited in claim 1, wherein the logic function is a NOR function.
Claim 8
Dependent Claim
283 words
An integrated circuit comprising a logic gate and a master gate, the logic gate having a logic threshold voltage, comprising: a logic function having at least one input and at least one output, and first and second power nodes; a first transistor having an input terminal and two output terminals, one output terminal connecting to a first power supply rail and the other connecting to the first power node; a second transistor having an input terminal and two output terminals, one output terminal connecting to a second power supply rail and the other connecting to the second power node; wherein the input terminals of the first and second transistors are connected together and couple to a control signal input for adjusting the logic threshold voltage of the logic gate; a master gate, generating the control signal at an output, comprising: first, second, third and fourth transistors, each having an input terminal and two outputs, the outputs serially connected between a first power supply rail and a second power supply rail, the connection between a middle two of the transistors being the output; wherein the master gate includes additional first and second conductivity transistors to implement the same logic function as the logic gate, and the input terminal of the second and third transistors being connected together and coupled to the output, the input terminal of the first and fourth transistors being connected together, the first and second transistors are of the first conductivity type and the third and fourth transistors are of the second conductivity type, and wherein the logic threshold voltage of the gate is substantially equal to a voltage applied to the input terminals of the first and fourth input terminals.
Claim 9
Dependent Claim
283 words
An integrated circuit comprising a logic gate and a master gate, the logic gate having a logic threshold voltage, comprising: a logic function having at least one input and at least one output, and first and second power nodes; a first transistor having an input terminal and two output terminals, one output terminal connecting to a first power supply rail and the other connecting to the first power node; a second transistor having an input terminal and two output terminals, one output terminal connecting to a second power supply rail and the other connecting to the second power node; wherein the input terminals of the first and second transistors are connected together and couple to a control signal input for adjusting the logic threshold voltage of the logic gate; a master gate, generating the control signal at an output, comprising: first, second, third and fourth transistors, each having an input terminal and two outputs, the outputs serially connected between a first power supply rail and a second power supply rail, the connection between a middle two of the transistors being the output; wherein the master gate includes additional first and second conductivity transistors to implement the same logic function as the logic gate, and the input terminal of the second and third transistors being connected together and coupled to the output, the input terminal of the first and fourth transistors being connected together, the first and second transistors are of the first conductivity type and the third and fourth transistors are of the second conductivity type, and wherein the logic threshold voltage of the gate is substantially equal to a voltage applied to the input terminals of the first and fourth input terminals.
Claim 10
Dependent Claim
25 words
The master gate as recited in claim 7, further characterized the first and fourth transistors being connected to the first and second power rails, respectively.
Claim 11
Dependent Claim
25 words
The master gate as recited in claim 7, further characterized the first and third transistors being connected to the first and second power rails, respectively.
Claim 12
Dependent Claim
25 words
The master gate as recited in claim 7, further characterized the second and third transistors being connected to the first and second power rails, respectively.
Claim 13
Dependent Claim
16 words
The logic gate as recited in claim 7, wherein the logic function is a NAND function.
Claim 14
Dependent Claim
16 words
The logic gate as recited in claim 7, wherein the logic function is a NOR function.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |