Semiconductor package and device having heads coupled with insulating material

Claim 2

A semiconductor device package comprising: a plurality of leads and a stage for mounting a semiconductor chip arranged in juxtaposition at predetermined spatial intervals; a protruded terminal formed at a predetermined portion on the lower surface of each of said leads; and an insulating material deposited in a continuous layer on the upper surfaces and the side surfaces of said plurality of leads and on the side surfaces of said stage; wherein: said plurality of leads and said protruded terminals on the lower surfaces of said leads are integrally formed from the same plate by separating a plurality of lead-forming portions of said plate into said plurality of leads and said protruded terminals on the lower surfaces of said leads; said plurality of leads and said stage are integrally coupled to each other through said insulating material; and the upper surfaces of said leads, the upper surface of said stage and said protruded terminals on the lower surfaces of said leads are exposed out of said insulating material.

Claim 3

A semiconductor device package according to claim 1, wherein the upper surfaces of said leads and the upper surface of said stage are plated for bonding.

Claim 4

A semiconductor device comprising a package according to claim 1 and a semiconductor chip bonded on the upper surface of the stage, the electrodes of said chip being electrically connected to the terminals on the upper surfaces of said leads, and the upper surface of said stage and the upper surfaces of said leads being deposited with a sealing insulating material thereby to seal said semiconductor chip in said sealing material.

Claim 5

A semiconductor device according to claim 3, wherein at least one of said protruded terminals on the lower surfaces of said leads and the lower surface of said stage is formed with a soldering bump.

Claim 6

A semiconductor device according to claim 4, wherein the upper surface of the semiconductor chip is exposed outside said sealing insulating material, and a heat spreader is placed on the upper surface of said semiconductor chip.

Claim 7

A semiconductor device package comprising: a plurality of leads arranged in juxtaposition at predetermined spatial intervals; a protruded terminal formed at a predetermined portion of the lower surface of each of said leads; and an insulating material deposited in a continuous layer on the upper surfaces and the side surfaces of said leads; wherein: said plurality of leads and said protruded terminals on the lower surfaces of said leads are integrally formed from the same plate by separating a plurality of lead-forming portions of said plate into said plurality of leads and said protruded terminals on the lower surfaces of said leads; said plurality of leads are integrally coupled to each other through said insulating material; and the upper surfaces of said leads and said protruded terminals are exposed out of said insulating material.

Claim 8

A semiconductor device package comprising: a plurality of leads arranged in juxtaposition at predetermined spatial intervals; a protruded terminal formed at a predetermined portion of the lower surface of each of said leads; and an insulating material deposited in a continuous layer on the upper surfaces and the side surfaces of said leads; wherein: said plurality of leads and said protruded terminals on the lower surfaces of said leads are integrally formed from the same plate by separating a plurality of lead-forming portions of said plate into said plurality of leads and said protruded terminals on the lower surfaces of said leads; said plurality of leads are integrally coupled to each other through said insulating material; and the upper surfaces of said leads and said protruded terminals are exposed out of said insulating material.

Claim 9

A semiconductor device package according to claim 6, wherein the upper surfaces of said leads are plated for bonding.

Claim 10

A semiconductor device comprising a package according to claim 6, and a semiconductor chip arranged above said leads, the electrodes of said chip being electrically connected to the terminals on the upper surfaces of said leads, and the upper surfaces of said leads being deposited with a sealing insulating material thereby to seal said semiconductor chip in said sealing insulating material.

Claim 11

A semiconductor device according to claim 8, wherein the terminals on the lower surfaces of said leads are each formed with a soldering bump.

Claim 12

A semiconductor device according to claim 9, wherein the upper surface of said semiconductor chip is exposed out of said sealing insulating material, and the upper surface of said semiconductor chip holds a heat spreader.

Claim 13

A semiconductor device according to claim 3, wherein the terminals on the lower surfaces of said leads and the lower surface of said stage are each formed with a soldering bump.

Claim 14

A semiconductor device according to claim 11, wherein the upper surface of the semiconductor chip is exposed outside said sealing insulating material, and the upper surface of said semiconductor chip is deposited with a heat spreader.

Claim 15

A semiconductor device according to claim 8, wherein the terminals on the lower surfaces of said leads are each formed with a soldering bump.

Claim 16

A semiconductor device according to claim 13, wherein the upper surface of the semiconductor chip is exposed outside said sealing insulating material, and the upper surface of said semiconductor chip holds a heat spreader.

Claim 17

A semiconductor device comprising: a plurality of leads and a stage for mounting a semiconductor chip arranged in juxtaposition at predetermined spatial intervals; a semiconductor chip having electrodes and arranged above said stage; terminals formed on the upper surfaces of said leads; a protruded terminal formed at a predetermined portion on the lower surface of each of said leads; and means for electrically connecting the electrodes of said semiconductor chip to the terminals on the upper surfaces of said leads; and an insulating material deposited in a continuous layer on the upper surfaces and the side surfaces of said plurality of leads, on the side surfaces of said stage, and on the upper surface of said semiconductor chip; wherein: said plurality of leads and said protruded terminals on the lower surfaces of said leads are integrally formed from the same plate by separating a plurality of lead-forming portions of said plate into said plurality of leads and said protruded terminals on the lower surfaces of said leads; said insulating material maintains said plurality of leads said protruded terminals on the lower surfaces of said leads, and said stage integrally coupled to each other and seals said semiconductor chip therein over said terminals on the upper surfaces of said plurality of leads and said stage; and said protruded terminals on the lower surfaces of said leads are exposed outside said insulating material.

Claim 18

A semiconductor device comprising: a plurality of leads and a stage for mounting a semiconductor chip arranged in juxtaposition at predetermined spatial intervals; a semiconductor chip having electrodes and arranged above said stage; terminals formed on the upper surfaces of said leads; a protruded terminal formed at a predetermined portion on the lower surface of each of said leads; and means for electrically connecting the electrodes of said semiconductor chip to the terminals on the upper surfaces of said leads; and an insulating material deposited in a continuous layer on the upper surfaces and the side surfaces of said plurality of leads, on the side surfaces of said stage, and on the upper surface of said semiconductor chip; wherein: said plurality of leads and said protruded terminals on the lower surfaces of said leads are integrally formed from the same plate by separating a plurality of lead-forming portions of said plate into said plurality of leads and said protruded terminals on the lower surfaces of said leads; said insulating material maintains said plurality of leads said protruded terminals on the lower surfaces of said leads, and said stage integrally coupled to each other and seals said semiconductor chip therein over said terminals on the upper surfaces of said plurality of leads and said stage; and said protruded terminals on the lower surfaces of said leads are exposed outside said insulating material.

Claim 19

A semiconductor device according to claim 15, wherein the terminals on the upper surfaces of said leads and the upper surface of said stage is plated for bonding.

Claim 20

A semiconductor device according to claim 15, wherein a soldering bump is formed on at least one of said protruded terminals formed on the lower surface of each of said leads and the lower surface of said stage.

Claim 21

A semiconductor device comprising: a plurality of leads arranged in juxtaposition at predetermined spatial intervals; terminals formed on the upper surfaces of said leads; a protruded terminal formed at a predetermined portion of the lower surface of each of said leads; a semiconductor chip having electrodes and arranged above said leads; means for electrically connecting the electrodes of said semiconductor chip to said terminals on the upper surfaces of said leads; and an insulating material deposited in a continuous layer on the upper surfaces and the side surfaces of said leads; wherein: said plurality of leads and said protruded terminals on the lower surfaces of said leads are integrally formed from the same plate by separating a plurality of lead-forming portions of said plate into said plurality of leads and said protruded terminals on the lower surfaces of said leads; said insulating material maintains said plurality of leads and said protruded terminals on the lower surfaces of said leads integrally coupled to each other and seals said semiconductor chip therein over said terminals on the upper surfaces of said leads; and said protruded terminals on the lower surfaces of said leads are exposed outside said insulating material.

Claim 22

A semiconductor device comprising: a plurality of leads arranged in juxtaposition at predetermined spatial intervals; terminals formed on the upper surfaces of said leads; a protruded terminal formed at a predetermined portion of the lower surface of each of said leads; a semiconductor chip having electrodes and arranged above said leads; means for electrically connecting the electrodes of said semiconductor chip to said terminals on the upper surfaces of said leads; and an insulating material deposited in a continuous layer on the upper surfaces and the side surfaces of said leads; wherein: said plurality of leads and said protruded terminals on the lower surfaces of said leads are integrally formed from the same plate by separating a plurality of lead-forming portions of said plate into said plurality of leads and said protruded terminals on the lower surfaces of said leads; said insulating material maintains said plurality of leads and said protruded terminals on the lower surfaces of said leads integrally coupled to each other and seals said semiconductor chip therein over said terminals on the upper surfaces of said leads; and said protruded terminals on the lower surfaces of said leads are exposed outside said insulating material.

Claim 23

A semiconductor device according to claim 18, wherein the terminals on the upper surfaces of said leads are plated for bonding.

Claim 24

A semiconductor device according to claim 18, wherein a soldering bump is formed on the protruded terminal formed on the lower surface of each of said leads.

Claim 25

A semiconductor device according to claim 18, wherein the upper surface of said semiconductor chip is exposed outside said insulating material, and a heat spreader is placed on the upper surface of said semiconductor chip.

Claim 26

A semiconductor device package according to claim 1, wherein: said plate is a single metal plate having upper and lower surfaces; said plurality of leads and said protruded terminals on the lower surfaces of said leads are formed by etching the upper and lower surfaces of said plate to separate said plurality of lead-forming portions of said plate into said plurality of leads and protruded terminals; said stage is formed by etching the upper surface of said plate to separate a stage-forming portion of said plate into said stage; and said insulating material is deposited on the etched upper surface of said plate before etching of the lower surface of said plate such that said insulating material maintains said plurality of leads, said protruded terminals on the lower surfaces of said leads, and said stage together during and after etching of said plate.

Claim 27

A semiconductor device package according to claim 6, wherein: said plate is a single metal plate having upper and lower surfaces; said plurality of leads and said protruded terminals on the lower surfaces of said leads are formed by etching the upper and lower surfaces of said plate to separate said plurality of lead-forming portions of said plate into said plurality of leads and protruded terminals; and said insulating material is deposited on the etched upper surface of said plate before etching of the lower surface of said plate such that said insulating material maintains said plurality of leads and said protruded terminals on the lower surfaces of said leads together during and after etching of said plate.

Claim 28

A semiconductor device according to claim 15, wherein: said plate is a single metal plate having upper and lower surfaces; said plurality of leads and said protruded terminals on the lower surfaces of said leads are formed by etching the upper and lower surfaces of said plate to separate said plurality of lead-forming portions of said plate into said plurality of leads and protruded terminals; said stage is formed by etching the upper surface of said plate to separate a stage-forming portion of said plate into said stage; and said insulating material is deposited on the etched upper surface of said plate before etching of the lower surface of said plate such that said insulating material maintains said plurality of leads, said protruded terminals on the lower surfaces of said leads, and said stage together during and after etching of said plate.

Claim 29

A semiconductor device according to claim 18, wherein: said plate is a single metal plate having upper and lower surfaces; said plurality of leads and said protruded terminals on the lower surfaces of said leads are formed by etching the upper and lower surfaces of said plate to separate said plurality of lead-forming portions of said plate into said plurality of leads and protruded terminals; and said insulating material is deposited on the upper surface of said plate before etching of the lower surface of said plate such that said insulating material maintains said plurality of leads and said protruded terminals on the lower surfaces of said leads together during and after etching of said plate.