US5847421A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic cell having efficient optical proximity effect correction
Assignee: Toshiba Corp
•
Filing: 1997-07-14
•
Granted: 1998-12-08
•
Expires: 2017-07-14
Abstract
Abstract There are provided a semiconductor device, basic cell library, a method for manufacturing a semiconductor device, and a method and mask for forming a basic cell library which can reduce the amount of poly-data to be corrected by the optical proximity effect correction (OPC), reduce the CAD processing time, perform correction by the OPC for each cell, and reduce the product turn around time. A basic cell registered in the basic cell library has a dummy wiring pattern previously formed on the peripheral portion thereof. With this structure, the distance between a polysilicon gate used in a circuit and the polysilicon wiring of an adjacent dummy wiring pattern in the basic cell can be determined in the cell. As a result, variations in the poly-widths of all of the polysilicon gates in the basic cell due to the optical proximity effect can be estimated, and therefore, a correction value by the OPC on a mask for correcting the gate width based on the variation in the poly-width can be determined in the cell.
Inventors
- 👤 Akira Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D89/00; H10D89/10; G; G03; G03F; G03F1/00; G03F1/36
Claims Analysis
Total Claims: 62
Claim 1
Independent Claim
36 words
A semiconductor device comprising: a semiconductor substrate; a logic circuit formed on the semiconductor substrate, the logic circuit including a gate electrode; and a dummy wiring pattern formed at a peripheral portion of the logic circuit.
Claim 2
Dependent Claim
36 words
A semiconductor device comprising: a semiconductor substrate; a logic circuit formed on the semiconductor substrate, the logic circuit including a gate electrode; and a dummy wiring pattern formed at a peripheral portion of the logic circuit.
Claim 3
Dependent Claim
36 words
The semiconductor device of claim 1, wherein the logic circuit is one of an AND gate circuit, a NAND gate circuit, an EX-OR gate circuit, a NOR gate circuit, an inverter circuit, and a flip-flop circuit.
Claim 4
Dependent Claim
27 words
The semiconductor device of claim 1, wherein a width of the gate electrode is dependent upon a distance between the gate electrode and the dummy wiring pattern.
Claim 5
Dependent Claim
36 words
The semiconductor device of claim 3, wherein the distance between the gate electrode and the dummy wiring pattern is predetermined and the width of the gate electrode is selected to compensate for an optical proximity effect.
Claim 6
Dependent Claim
21 words
The semiconductor device of claim 1, wherein a width of the gate electrode is less than or equal to 0.3 μm.
Claim 7
Dependent Claim
25 words
The semiconductor device of claim 1, wherein a width of the gate electrode is substantially the same as a width of the dummy wiring pattern.
Claim 8
Dependent Claim
23 words
The semiconductor device of claim 1, wherein a width of the gate electrode is different than a width of the dummy wiring pattern.
Claim 9
Dependent Claim
19 words
The semiconductor device of claim 1, wherein the gate electrode and the dummy wiring pattern are formed of polysilicon.
Claim 10
Dependent Claim
16 words
The semiconductor device of claim 1, wherein the dummy wiring pattern completely surrounds the logic circuit.
Claim 11
Dependent Claim
20 words
The semiconductor device of claim 1, wherein the dummy wiring pattern is parallel to a length of the gate electrode.
Claim 12
Dependent Claim
18 words
The semiconductor device of claim 1, wherein the dummy wiring pattern comprises a plurality of dummy wiring portions.
Claim 13
Dependent Claim
54 words
A semiconductor device comprising: a semiconductor substrate; a plurality of logic circuits formed on the semiconductor substrate, each of the plurality of logic circuits including a gate electrode; and a dummy wiring pattern formed at a peripheral portion of the plurality of logic circuits and between adjacent ones of the plurality of logic circuits.
Claim 14
Dependent Claim
54 words
A semiconductor device comprising: a semiconductor substrate; a plurality of logic circuits formed on the semiconductor substrate, each of the plurality of logic circuits including a gate electrode; and a dummy wiring pattern formed at a peripheral portion of the plurality of logic circuits and between adjacent ones of the plurality of logic circuits.
Claim 15
Dependent Claim
40 words
The semiconductor device of claim 12, wherein each of the plurality of logic circuits is one of an AND gate circuit, a NAND gate circuit, an EX-OR gate circuit, a NOR gate circuit, an inverter circuit, and a flip-flop circuit.
Claim 16
Dependent Claim
29 words
The semiconductor device of claim 12, wherein a width of each of the gate electrodes is dependent upon a distance between the gate electrode and the dummy wiring pattern.
Claim 17
Dependent Claim
36 words
The semiconductor device of claim 14, wherein the distance between the gate electrode and the dummy wiring pattern is predetermined and the width of each gate electrode is selected to compensate for an optical proximity effect.
Claim 18
Dependent Claim
23 words
The semiconductor device of claim 12, wherein a width of each of the gate electrodes is less than or equal to 0.3 μm.
Claim 19
Dependent Claim
27 words
The semiconductor device of claim 12, wherein a width of each of the gate electrodes is substantially the same as a width of the dummy wiring pattern.
Claim 20
Dependent Claim
25 words
The semiconductor device of claim 12, wherein a width of each of the gate electrodes is different than a width of the dummy wiring pattern.
Claim 21
Dependent Claim
19 words
The semiconductor device of claim 12, wherein the gate electrodes and the dummy wiring pattern are formed of polysilicon.
Claim 22
Dependent Claim
18 words
The semiconductor device of claim 12, wherein the dummy wiring pattern completely surrounds the plurality of logic circuits.
Claim 23
Dependent Claim
22 words
The semiconductor device of claim 12, wherein the dummy wiring pattern is parallel to a length of each of the gate electrodes.
Claim 24
Dependent Claim
18 words
The semiconductor device of claim 12, wherein the dummy wiring pattern comprises a plurality of dummy wiring portions.
Claim 25
Dependent Claim
70 words
A logic cell library comprising: a plurality of logic cells, each logic cell including a logic circuit including a gate electrode, and a dummy wiring pattern located at a peripheral portion of the logic circuit; wherein a distance between the gate electrode and the dummy wiring pattern of each logic circuit cell is predetermined and the width of the gate electrode is selected to compensate for an optical proximity effect.
Claim 26
Dependent Claim
70 words
A logic cell library comprising: a plurality of logic cells, each logic cell including a logic circuit including a gate electrode, and a dummy wiring pattern located at a peripheral portion of the logic circuit; wherein a distance between the gate electrode and the dummy wiring pattern of each logic circuit cell is predetermined and the width of the gate electrode is selected to compensate for an optical proximity effect.
Claim 27
Dependent Claim
51 words
The cell library of claim 23, wherein the logic circuit of each logic cell is one of an AND gate circuit, a NAND gate circuit, an EX-OR gate circuit, a NOR gate circuit, an inverter circuit, and a flip-flop circuit, and wherein each logic cell corresponds to a different logic circuit.
Claim 28
Dependent Claim
29 words
The cell library of claim 23, wherein a width of each of the gate electrodes is dependent upon a distance between the gate electrode and the dummy wiring pattern.
Claim 29
Dependent Claim
23 words
The cell library of claim 23, wherein a width of each of the gate electrodes is less than or equal to 0.3 μm.
Claim 30
Dependent Claim
27 words
The cell library of claim 23, wherein a width of each of the gate electrodes is substantially the same as a width of the dummy wiring pattern.
Claim 31
Dependent Claim
25 words
The cell library of claim 23, wherein a width of each of the gate electrodes is different than a width of the dummy wiring pattern.
Claim 32
Dependent Claim
19 words
The cell library of claim 23, wherein the gate electrodes and the dummy wiring pattern are formed of polysilicon.
Claim 33
Dependent Claim
16 words
The cell library of claim 23, wherein the dummy wiring pattern completely surrounds the logic circuit.
Claim 34
Dependent Claim
22 words
The cell library of claim 23, wherein the dummy wiring pattern is parallel to a length of each of the gate electrodes.
Claim 35
Dependent Claim
18 words
The cell library of claim 23, wherein the dummy wiring pattern comprises a plurality of dummy wiring portions.
Claim 36
Dependent Claim
93 words
A logic cell library comprising: a plurality of logic cells, at least one of the logic cells including a plurality of logic circuits, each including a gate electrode, and a dummy wiring pattern located at a peripheral portion of the plurality of logic circuits and located between adjacent ones of the plurality of logic circuits; wherein a distance between the gate electrode of each of the plurality of logic circuits and the dummy wiring pattern is predetermined and the width of each gate electrode is selected to compensate for an optical proximity effect.
Claim 37
Dependent Claim
93 words
A logic cell library comprising: a plurality of logic cells, at least one of the logic cells including a plurality of logic circuits, each including a gate electrode, and a dummy wiring pattern located at a peripheral portion of the plurality of logic circuits and located between adjacent ones of the plurality of logic circuits; wherein a distance between the gate electrode of each of the plurality of logic circuits and the dummy wiring pattern is predetermined and the width of each gate electrode is selected to compensate for an optical proximity effect.
Claim 38
Dependent Claim
40 words
The cell library of claim 33, wherein each of the plurality of logic circuits is one of an AND gate circuit, a NAND gate circuit, an EX-OR gate circuit, a NOR gate circuit, an inverter circuit, and a flip-flop circuit.
Claim 39
Dependent Claim
29 words
The cell library of claim 33, wherein a width of each of the gate electrodes is dependent upon a distance between the gate electrode and the dummy wiring pattern.
Claim 40
Dependent Claim
23 words
The cell library of claim 33, wherein a width of each of the gate electrodes is less than or equal to 0.3 μm.
Claim 41
Dependent Claim
27 words
The cell library of claim 33, wherein a width of each of the gate electrodes is substantially the same as a width of the dummy wiring pattern.
Claim 42
Dependent Claim
25 words
The cell library of claim 33, wherein a width of each of the gate electrodes is different than a width of the dummy wiring pattern.
Claim 43
Dependent Claim
19 words
The cell library of claim 33, wherein the gate electrodes and the dummy wiring pattern are formed of polysilicon.
Claim 44
Dependent Claim
18 words
The cell library of claim 33, wherein the dummy wiring pattern completely surrounds the plurality of logic circuits.
Claim 45
Dependent Claim
22 words
The cell library of claim 33, wherein the dummy wiring pattern is parallel to a length of each of the gate electrodes.
Claim 46
Dependent Claim
18 words
The cell library of claim 33, wherein the dummy wiring pattern comprises a plurality of dummy wiring portions.
Claim 47
Dependent Claim
62 words
A semiconductor integrated circuit, comprising: a semiconductor substrate; a logic circuit formed on the semiconductor substrate and including a gate electrode; and a dummy wiring pattern formed at a peripheral portion of the logic circuit, said dummy wiring pattern including first and second wiring patterns located on opposite sides of the gate electrode and parallel to a length of the gate electrode.
Claim 48
Dependent Claim
62 words
A semiconductor integrated circuit, comprising: a semiconductor substrate; a logic circuit formed on the semiconductor substrate and including a gate electrode; and a dummy wiring pattern formed at a peripheral portion of the logic circuit, said dummy wiring pattern including first and second wiring patterns located on opposite sides of the gate electrode and parallel to a length of the gate electrode.
Claim 49
Dependent Claim
23 words
The semiconductor integrated circuit of claim 43, wherein each of the first and second wiring patterns comprises a plurality of dummy wiring portions.
Claim 50
Dependent Claim
18 words
The semiconductor integrated circuit of claim 43, wherein each of the first and second wiring patterns is continuous.
Claim 51
Dependent Claim
35 words
The semiconductor integrated circuit of claim 43, further including third and fourth wiring patterns perpendicular to and contiguous with the first and second wiring patterns, so that said dummy wiring pattern surrounds said logic circuit.
Claim 52
Dependent Claim
62 words
A semiconductor integrated circuit, comprising: a semiconductor substrate; a logic circuit formed on the semiconductor substrate and including first and second gate electrodes; and a dummy wiring pattern formed at a peripheral portion of the logic circuit, said dummy wiring pattern including first and second wiring patterns respectively located parallel to a length of each of the first and second gate electrodes.
Claim 53
Dependent Claim
62 words
A semiconductor integrated circuit, comprising: a semiconductor substrate; a logic circuit formed on the semiconductor substrate and including first and second gate electrodes; and a dummy wiring pattern formed at a peripheral portion of the logic circuit, said dummy wiring pattern including first and second wiring patterns respectively located parallel to a length of each of the first and second gate electrodes.
Claim 54
Dependent Claim
23 words
The semiconductor integrated circuit of claim 47, wherein each of the first and second wiring patterns comprises a plurality of dummy wiring portions.
Claim 55
Dependent Claim
18 words
The semiconductor integrated circuit of claim 47, wherein each of the first and second wiring patterns is continuous.
Claim 56
Dependent Claim
35 words
The semiconductor integrated circuit of claim 47, further including third and fourth wiring patterns perpendicular to and contiguous with the first and second wiring patterns, so that said dummy wiring pattern surrounds said logic circuit.
Claim 57
Dependent Claim
113 words
A semiconductor integrated circuit, comprising: a semiconductor substrate; a first logic circuit formed on the semiconductor substrate and including a first gate electrode; a second logic circuit formed on the semiconductor substrate next to the first logic circuit and including a second gate electrode parallel to the first gate electrode; a first dummy wiring pattern located at a peripheral portion of the first logic circuit remote from the second logic circuit and parallel to a length of the first gate electrode; and a second dummy wiring pattern located at a peripheral portion of the second logic circuit remote from the first logic circuit and parallel to a length of the second gate electrode.
Claim 58
Dependent Claim
113 words
A semiconductor integrated circuit, comprising: a semiconductor substrate; a first logic circuit formed on the semiconductor substrate and including a first gate electrode; a second logic circuit formed on the semiconductor substrate next to the first logic circuit and including a second gate electrode parallel to the first gate electrode; a first dummy wiring pattern located at a peripheral portion of the first logic circuit remote from the second logic circuit and parallel to a length of the first gate electrode; and a second dummy wiring pattern located at a peripheral portion of the second logic circuit remote from the first logic circuit and parallel to a length of the second gate electrode.
Claim 59
Dependent Claim
24 words
The semiconductor integrated circuit of claim 51, wherein each of the first and second dummy wiring patterns comprises a plurality of dummy wiring portions.
Claim 60
Dependent Claim
18 words
The semiconductor integrated circuit of claim 51, wherein each of the first and second wiring patterns is continuous.
Claim 61
Dependent Claim
31 words
The semiconductor integrated circuit of claim 51, further including a third dummy wiring pattern located between the first and second logic circuits and parallel to the first and second gate electrodes.
Claim 62
Dependent Claim
34 words
The semiconductor integrated circuit of claim 54, further including fourth and fifth dummy wiring patterns perpendicular to and contiguous with first and second ends, respectively, of the first, second and third dummy wiring patterns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |