Patent US6388539B1 successfully refreshed from Google Patents.
US5845233A
Expired / Lapsed
US
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Method and apparatus for calibrating static timing analyzer to path delay measurements
Assignee: Nokia of America Corp
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Filing: 1997-07-30
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Granted: 1998-12-01
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Expires: 2017-07-30
Abstract
Abstract A method for calibrating a circuit analyzer includes determining a plurality of initial technology parameters characterizing the circuit according to a timing model of the circuit. A delay along an entire logic path of the circuit is expressed as a function of the technology parameters. A benchmark set of circuit paths is determined which has fixed topology, device sizes, and wire capacitances. The technology parameters are then optimized to minimize error over the set of circuit paths to obtain optimized parameters for use in the timing model. The optimized technology parameters minimize the average error for the benchmark set of paths relative to SPICE or physical measurements. Average error is significantly reduced on a representative set of paths when compared to the conventional approach of separately measuring each parameter.
Inventors
- 👤 John Philip Fishburn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:10
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/3312; G06F30/36; G06F30/367
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
85 words
A method of calibrating a circuit analyzer, comprising: determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit; expressing a delay along an entire logic path of said circuit as a function of said technology parameters; determining a set of circuit paths having fixed topology, device sizes, and wire capacitances; and optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.
Claim 2
Independent Claim
85 words
A method of calibrating a circuit analyzer, comprising: determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit; expressing a delay along an entire logic path of said circuit as a function of said technology parameters; determining a set of circuit paths having fixed topology, device sizes, and wire capacitances; and optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.
Claim 3
Dependent Claim
27 words
A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes minimizing a sum of squares of said plurality of errors.
Claim 4
Dependent Claim
55 words
A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes varying said plurality of technology parameters within an optimization program to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on actual measurement.
Claim 5
Dependent Claim
55 words
A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes varying said plurality of technology parameters within an optimization program to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on circuit simulation.
Claim 6
Dependent Claim
24 words
A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes constraining said plurality of errors as conservative.
Claim 7
Independent Claim
96 words
An apparatus for calibrating a circuit analyzer, comprising: means for determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit; means for expressing a delay along an entire logic path of said circuit as a function of said technology parameters; means for determining a set of circuit paths having fixed topology, device sizes, and wire capacitances; and a processor including means for optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.
Claim 8
Independent Claim
96 words
An apparatus for calibrating a circuit analyzer, comprising: means for determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit; means for expressing a delay along an entire logic path of said circuit as a function of said technology parameters; means for determining a set of circuit paths having fixed topology, device sizes, and wire capacitances; and a processor including means for optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.
Claim 9
Dependent Claim
24 words
An apparatus according to claim 6, wherein said means for optimizing includes means for minimizing a sum of squares of said plurality of errors.
Claim 10
Dependent Claim
48 words
An apparatus according to claim 6, wherein said means for optimizing includes means for varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on actual measurement.
Claim 11
Dependent Claim
48 words
An apparatus according to claim 6, wherein said means for optimizing includes means for varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on circuit simulation.
Claim 12
Dependent Claim
21 words
An apparatus according to claim 6, wherein said means for optimizing includes means for constraining said plurality of errors as conservative.
Claim 13
Dependent Claim
145 words
A circuit analyzer for generating a graphic representation of a predicted performance of a circuit, the circuit analyzer comprising: an input device for inputting a plurality of circuit parameters representing said circuit; memory and stored programs for receiving and storing said circuit parameters; a processor that is controlled by said stored programs and accesses said circuit parameters such that said processor: expresses a delay along an entire logic path of said circuit as a function of said circuit parameters, determines a set of circuit paths having fixed topology, device sizes, and wire capacitances, determines said circuit parameters to predict the performance of the circuit, and determines optimum circuit parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said processing means; and an output device that generates a graphic representation from said processed circuit parameters.
Claim 14
Dependent Claim
145 words
A circuit analyzer for generating a graphic representation of a predicted performance of a circuit, the circuit analyzer comprising: an input device for inputting a plurality of circuit parameters representing said circuit; memory and stored programs for receiving and storing said circuit parameters; a processor that is controlled by said stored programs and accesses said circuit parameters such that said processor: expresses a delay along an entire logic path of said circuit as a function of said circuit parameters, determines a set of circuit paths having fixed topology, device sizes, and wire capacitances, determines said circuit parameters to predict the performance of the circuit, and determines optimum circuit parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said processing means; and an output device that generates a graphic representation from said processed circuit parameters.
Claim 15
Dependent Claim
25 words
An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by minimizing a sum of squares of said plurality of errors.
Claim 16
Dependent Claim
49 words
An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on actual measurement.
Claim 17
Dependent Claim
49 words
An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on circuit simulation.
Claim 18
Dependent Claim
22 words
An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by constraining said plurality of errors as conservative.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |