Method and apparatus for programming anti-fuses

Claim 2

A programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in an integrated circuit, comprising: a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a first programming voltage having a positive polarity; a second external terminal of the integrated circuit adapted to receive a second programming voltage having a negative polarity: and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active, and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive.

Claim 3

The circuit of claim 1 wherein the first programming voltage is applied to the first terminal from a source external to the integrated circuit.

Claim 4

The circuit of claim 1 wherein there is substantially no voltage drop across the voltage translation circuit so that substantially the full magnitude of the second programming voltage on the second external terminal is applied to the second terminal of the anti-fuse.

Claim 5

A programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising: a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a first programming voltage having a predetermined polarity; a second external terminal of the integrated circuit adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage; and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive, the voltage translation circuit including, a control circuit which operates to couple the second external terminal to a pass terminal when the enable signal is active and to couple the second external terminal to a control terminal when the enable signal is inactive to thereby provide the second programming voltage on the pass and control terminals, respectively; a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active; and a reset circuit coupled to the enable terminal and the control terminal and having a reset terminal coupled to the input terminal of the pass circuit, the reset circuit operable to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the second programming voltage on the control terminal, and operable to isolate the reset terminal when the enable signal is inactive.

Claim 6

A programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising: a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a first programming voltage having a predetermined polarity; a second external terminal of the integrated circuit adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage; and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive, the voltage translation circuit including, a control circuit which operates to couple the second external terminal to a pass terminal when the enable signal is active and to couple the second external terminal to a control terminal when the enable signal is inactive to thereby provide the second programming voltage on the pass and control terminals, respectively; a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active; and a reset circuit coupled to the enable terminal and the control terminal and having a reset terminal coupled to the input terminal of the pass circuit, the reset circuit operable to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the second programming voltage on the control terminal, and operable to isolate the reset terminal when the enable signal is inactive.

Claim 7

The circuit of claim 4 wherein the control circuit comprises: a PMOS transistor having gate, source, and drain terminals, the enable terminal coupled through an inverter to the gate terminal and the source terminal coupled to a positive supply voltage; a first NMOS transistor having gate, source, and drain terminals, the gate terminal coupled to the gate terminal of the PMOS transistor and the drain terminal coupled to the drain of the PMOS transistor; and a second NMOS transistor having gate, source, and drain terminals, the gate terminal coupled to the drain terminal of the PMOS transistor, the drain terminal coupled to source terminal of the first NMOS transistor, and the source terminal coupled to input terminal of the pass circuit.

Claim 8

The circuit of claim 4 wherein the pass circuit comprises an NMOS transistor.

Claim 9

The circuit of claim 4 wherein the reset circuit comprises a PMOS transistor having a gate terminal coupled to the control terminal and an NMOS transistor having the enable terminal coupled through an inverter to a gate terminal, the PMOS and NMOS transistors having source and drain terminals connected, respectively, in series between the reset terminal and the common voltage reference.

Claim 10

A programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising: a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a positive programming voltage; an external terminal of the integrated circuit adapted to receive a negative programming voltage; an enable terminal adapted to receive an enable signal; and a voltage translation circuit coupled to the external terminal, the enable terminal, and the second terminal of the anti-fuse, comprising, a control circuit which operates to couple the external terminal to a pass terminal when the enable signal is active and to couple the external terminal to a control terminal when the enable signal is inactive to thereby provide the negative programing voltage on the pass and control terminals, respectively, a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active, and a reset circuit having a reset terminal coupled to the input terminal of the pass circuit, operable in a first mode to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the negative programming voltage on the control terminal, and operable in a second mode to provide a high impedance at the reset terminal when the enable signal is active and no negative programming voltage is provided on the control terminal.

Claim 11

A programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising: a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a positive programming voltage; an external terminal of the integrated circuit adapted to receive a negative programming voltage; an enable terminal adapted to receive an enable signal; and a voltage translation circuit coupled to the external terminal, the enable terminal, and the second terminal of the anti-fuse, comprising, a control circuit which operates to couple the external terminal to a pass terminal when the enable signal is active and to couple the external terminal to a control terminal when the enable signal is inactive to thereby provide the negative programing voltage on the pass and control terminals, respectively, a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active, and a reset circuit having a reset terminal coupled to the input terminal of the pass circuit, operable in a first mode to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the negative programming voltage on the control terminal, and operable in a second mode to provide a high impedance at the reset terminal when the enable signal is active and no negative programming voltage is provided on the control terminal.

Claim 12

The circuit of claim 8 wherein the control circuit comprises: a PMOS transistor having gate, source, and drain terminals, the enable terminal coupled through an inverter to the gate terminal and the source terminal coupled to a positive supply voltage; a first NMOS transistor having gate, source, and drain terminals, the gate terminal coupled to the gate terminal of the PMOS transistor and the drain terminal coupled to the drain of the PMOS transistor; and a second NMOS transistor having gate, source, and drain terminals, the gate terminal coupled to the drain terminal of the PMOS transistor, the drain terminal coupled to source terminal of the first NMOS transistor, and the source terminal coupled to input terminal of the pass circuit.

Claim 13

The circuit of claim 8 wherein the pass circuit comprises an NMOS transistor.

Claim 14

The circuit of claim 8 wherein the reset circuit comprises a PMOS transistor having a gate terminal coupled to the control terminal and an NMOS transistor having the enable terminal coupled through an inverter to a gate terminal, the PMOS and NMOS transistors having source and drain terminals connected in series, respectively, between the reset terminal and the reference voltage.

Claim 15

A dynamic random access memory, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a control circuit coupled the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a programming circuit for programming an anti-fuse having first and second terminals, comprising, a first terminal of the dynamic random access memory coupled to the first terminal of the anti-fuse, the first external terminal adapted to receive a first programming voltage having a positive polarity, a second external terminal of the dynamic random access memory adapted to receive a second programming voltage having a negative polarity, and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive.

Claim 16

A dynamic random access memory, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a control circuit coupled the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a programming circuit for programming an anti-fuse having first and second terminals, comprising, a first terminal of the dynamic random access memory coupled to the first terminal of the anti-fuse, the first external terminal adapted to receive a first programming voltage having a positive polarity, a second external terminal of the dynamic random access memory adapted to receive a second programming voltage having a negative polarity, and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive.

Claim 17

A dynamic random access memory, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a control circuit coupled the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, and a programming circuit for programming an anti-fuse having first and second terminals, comprising, a first external terminal of the dynamic random access memory coupled to the first terminal of the anti-fuse, the first external terminal adapted to receive a first programming voltage having a predetermined polarity, a second external terminal of the dynamic random access memory adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage, and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive, the voltage translation circuit comprising, a control circuit which operates to couple the second external terminal to a pass terminal when the enable signal is active and to couple the second external terminal to a control terminal when the enable signal is inactive to thereby provide the second programming voltage on the pass and control terminals, respectively, a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active, and a reset circuit having a reset terminal coupled to the input terminal of the pass circuit, operable in a first mode to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the negative programming voltage on the control terminal, and operable in a second mode to provide a high impedance at the reset terminal when the enable signal is active and no negative programming voltage is provided on the control terminal.

Claim 18

A dynamic random access memory, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a control circuit coupled the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, and a programming circuit for programming an anti-fuse having first and second terminals, comprising, a first external terminal of the dynamic random access memory coupled to the first terminal of the anti-fuse, the first external terminal adapted to receive a first programming voltage having a predetermined polarity, a second external terminal of the dynamic random access memory adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage, and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive, the voltage translation circuit comprising, a control circuit which operates to couple the second external terminal to a pass terminal when the enable signal is active and to couple the second external terminal to a control terminal when the enable signal is inactive to thereby provide the second programming voltage on the pass and control terminals, respectively, a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active, and a reset circuit having a reset terminal coupled to the input terminal of the pass circuit, operable in a first mode to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the negative programming voltage on the control terminal, and operable in a second mode to provide a high impedance at the reset terminal when the enable signal is active and no negative programming voltage is provided on the control terminal.

Claim 19

The dynamic random access memory of claim 13 wherein the control circuit comprises: a PMOS transistor having gate, source, and drain terminals, the enable terminal coupled through an inverter to the gate terminal and the source terminal coupled to a positive supply voltage; a first NMOS transistor having gate, source, and drain terminals, the gate terminal coupled to the gate terminal of the PMOS transistor and the drain terminal coupled to the drain of the PMOS transistor; and a second NMOS transistor having gate, source, and drain terminals, the gate terminal coupled to the drain terminal of the PMOS transistor, the drain terminal coupled to source terminal of the first NMOS transistor, and the source terminal coupled to input terminal of the pass circuit.

Claim 20

The dynamic random access memory of claim 14 wherein the pass circuit comprises an NMOS transistor.

Claim 21

The dynamic random access memory of claim 13 wherein the reset circuit comprises a PMOS transistor having a gate terminal coupled to the control terminal and an NMOS transistor having the enable terminal coupled through an inverter to a gate terminal, the PMOS and NMOS transistors having source and drain terminals connected, respectively, in series between the reset terminal and the common voltage reference.

Claim 22

The dynamic random access memory of claim 12 wherein each memory cell comprises: a storage element having a first storage terminal and a second storage terminal, the second storage terminal coupled to a reference voltage source of approximately V CC /2; and a memory switch circuit having a control terminal coupled to an associated row line, a first data terminal coupled to the first storage terminal of the storage element, and a second data terminal coupled to one of the associated first and second complementary digit lines.

Claim 23

A computer system, comprising: a data input device; a data output device; and computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes a programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising, a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a first programming voltage having a positive polarity, a second external terminal of the integrated circuit adapted to receive a second programing voltage having a negative polarity; and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive.

Claim 24

A computer system, comprising: a data input device; a data output device; and computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes a programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising, a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a first programming voltage having a positive polarity, a second external terminal of the integrated circuit adapted to receive a second programing voltage having a negative polarity; and a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive.

Claim 27

The method of claim 19 wherein the step of applying a first programming voltage includes the step of applying the first programming voltage to the first terminal of the anti-fuse from a source external to the integrated circuit.

Claim 28

The method of claim 19 wherein the step of applying a first programming voltage includes the step of applying a first programming voltage having a positive polarity.

Claim 29

The method of claim 19 wherein the step of applying a second programming voltage includes the step of applying a second programming voltage having a negative polarity.

Claim 30

The method of claim 19 wherein the step of coupling the second programming voltage includes the steps of: coupling the external terminal to a pass node in the first operating mode; coupling the external terminal to a control node in the second operating mode; coupling the pass node to the second terminal of the anti-fuse in the first operating mode; isolating the pass node from the second terminal of the anti-fuse in the second operating mode; coupling the pass node to a reference voltage in the second operating mode; and isolating the pass node from the reference voltage in the first operating mode.