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US5844270A Expired / Lapsed US ⏱️ 0.0 years remaining

Flash memory device and manufacturing method therefor

Assignee: Samsung Electronics Co Ltd
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Filing: 1996-12-12
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Granted: 1998-12-01
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Expires: 2016-12-12
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Abstract

Abstract A highly integrated flash memory device having a stable cell is provided. The device includes a semiconductor substrate of a first conductive type; a field insulating layer buried in a first trench formed in the semiconductor substrate in order to define an active region; a tunnel insulating film formed on the active region; a first conductive layer for a floating gate formed on the tunnel insulating film; spacers formed on both the tunnel insulating film and the sidewalls of the first conductive layer; a buried insulating layer buried in a second trench formed by etching the substrate adjacent to the spacers; a buried junction layer contacting a lower portion and sidewalls of the buried insulating layer, and acting as a source and drain region including impurities of a second conductive type; a second conductive layer formed on the first conductive layer and connected to the first conductive layer to be used as a floating gate; an insulating layer formed on the second conductive layer; and a third conductive layer for a control gate formed on the insulating layer. Accordingly, the flash memory device has a cell capable of maintaining stable operation and is appropriate for high-integration.

Inventors

  • 👤 Keon-Soo Kim
  • 👤 Yong-bae Choi
  • 👤 Jong-weon Yoo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 17:03
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 168 words
A flash memory device comprising: a semiconductor substrate of a first conductive type; a field insulating layer buried in a first trench formed in said semiconductor substrate in order to define an active region; a tunnel insulating film formed on said active region; a first conductive layer for a floating gate formed on said tunnel insulating film; spacers formed on both said tunnel insulating film and the sidewalls of said first conductive layer; a buried insulating layer buried in a second trench formed by etching said substrate adjacent to said spacers; a buried junction layer contacting a lower portion and sidewalls of said buried insulating layer, and acting as a source and drain region including impurities of a second conductive type; a second conductive layer formed on said first conductive layer and connected to said first conductive layer to be used as a floating gate; an insulating layer formed on said second conductive layer; and a third conductive layer for a control gate formed on said insulating layer.
Claim 2
Dependent Claim 168 words
A flash memory device comprising: a semiconductor substrate of a first conductive type; a field insulating layer buried in a first trench formed in said semiconductor substrate in order to define an active region; a tunnel insulating film formed on said active region; a first conductive layer for a floating gate formed on said tunnel insulating film; spacers formed on both said tunnel insulating film and the sidewalls of said first conductive layer; a buried insulating layer buried in a second trench formed by etching said substrate adjacent to said spacers; a buried junction layer contacting a lower portion and sidewalls of said buried insulating layer, and acting as a source and drain region including impurities of a second conductive type; a second conductive layer formed on said first conductive layer and connected to said first conductive layer to be used as a floating gate; an insulating layer formed on said second conductive layer; and a third conductive layer for a control gate formed on said insulating layer.
Claim 3
Dependent Claim 23 words
A flash memory device according to claim 1, wherein said insulating layer is formed of a composite film of oxide/nitride/oxide film (ONO film).
Claim 4
Dependent Claim 21 words
A flash memory device according to claim 1, wherein said first and second conductive layers are formed of a polysilicon film.
Claim 5
Dependent Claim 24 words
A flash memory device according to claim 1, wherein said first conductive type is a P-type and said second conductive type is an N-type.
Claim 6
Dependent Claim 24 words
A flash memory device according to claim 1, wherein a depth of said first trench is greater than a depth of said second trench.
Claim 7
Dependent Claim 178 words
A flash memory device comprising: a semiconductor substrate of a first conductive type; a field insulating layer buried in a trench formed on said semiconductor substrate of a first conductive type in order to define an active region; a tunnel insulating film formed on said active region; first and second conductive layers which are patterned to define a plurality of floating gates which extend on said tunnel insulating film and said field insulating layer; an insulating layer formed on said second conductive layer; a third conductive layer for a control gate formed on said insulating layer; a first impurity layer for cell channel stop regions formed of impurities of a first conductive type in said semiconductor substrate, said channel stop regions extending between said floating gates formed on said tunnel insulating film; and a second impurity layer for a source/drain region of a select transistor of a second conductive type, opposite to said first conductive type, in said semiconductor substrate, said source/drain region of the select transistor extending between said floating gates formed on said field insulating layer.
Claim 8
Dependent Claim 178 words
A flash memory device comprising: a semiconductor substrate of a first conductive type; a field insulating layer buried in a trench formed on said semiconductor substrate of a first conductive type in order to define an active region; a tunnel insulating film formed on said active region; first and second conductive layers which are patterned to define a plurality of floating gates which extend on said tunnel insulating film and said field insulating layer; an insulating layer formed on said second conductive layer; a third conductive layer for a control gate formed on said insulating layer; a first impurity layer for cell channel stop regions formed of impurities of a first conductive type in said semiconductor substrate, said channel stop regions extending between said floating gates formed on said tunnel insulating film; and a second impurity layer for a source/drain region of a select transistor of a second conductive type, opposite to said first conductive type, in said semiconductor substrate, said source/drain region of the select transistor extending between said floating gates formed on said field insulating layer.
Claim 9
Dependent Claim 24 words
A flash memory device according to claim 6, wherein said first conductive type is a P-type and said second conductive type is an n-type.
Claim 10
Dependent Claim 181 words
A flash memory device comprising: a semiconductor substrate of a first conductive type; a field insulating layer buried in a first trench formed in said semiconductor substrate of a first conductive type in order to define an active region; a tunnel insulating film formed on said active region; first and second conductive layers which are patterned to define a plurality of floating gates which extend on said tunnel insulating film and said field insulating layer; an insulating layer formed on said second conductive layer; a third conductive layer for a control gate formed on said insulating layer; a first impurity layer for cell channel stop regions formed of impurities of a first conductive type in a lower portion of a second trench formed by etching said semiconductor substrate between adjacent ones of said floating gates formed on said tunnel insulating layer; and a second impurity layer for a source and drain of a select transistor formed of a second conductive type, opposite to said first conductive type, in said semiconductor substrate between respective floating gates formed on said field insulating layer.
Claim 11
Dependent Claim 181 words
A flash memory device comprising: a semiconductor substrate of a first conductive type; a field insulating layer buried in a first trench formed in said semiconductor substrate of a first conductive type in order to define an active region; a tunnel insulating film formed on said active region; first and second conductive layers which are patterned to define a plurality of floating gates which extend on said tunnel insulating film and said field insulating layer; an insulating layer formed on said second conductive layer; a third conductive layer for a control gate formed on said insulating layer; a first impurity layer for cell channel stop regions formed of impurities of a first conductive type in a lower portion of a second trench formed by etching said semiconductor substrate between adjacent ones of said floating gates formed on said tunnel insulating layer; and a second impurity layer for a source and drain of a select transistor formed of a second conductive type, opposite to said first conductive type, in said semiconductor substrate between respective floating gates formed on said field insulating layer.
Claim 12
Dependent Claim 24 words
A flash memory device according to claim 8, wherein said first conductive type is a P-type, and said second conductive type is an N-type.
Claim 13
Dependent Claim 18 words
A flash memory device according to claim 8, wherein said first trench is deeper than said second trench.

References Cited (Backward Citations)

US5610420A Cited
US5610419A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-11-30 2002-06-01 2002-12-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-11-30 2006-06-01 2006-12-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-11-30 2010-06-01 2010-12-01 $7700.00 Window Closed / Lapsed

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