Abstract Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31 0 -31 n ,32 0 -= n , 33 0 -33 n , 34 0 -34 n ) coupled thereto which, in response to a control signal (b 0 -b n ) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a fist embodiment, the control signals (b 0 -b n ) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47 0 -47 n ) and the capacitors (53 0 -53 n ), respectively, are coupled in a capacitance charging circuit (47 0 -47 n , 43; 52, 53 0 -53 n ), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus. By coupling the apparatus in a ring configuration (FIG. 6), a counter unit (63), counting the number of signal delays through the delay apparatus (61) can lengthen the programmed time delay.
A programmable time delay apparatus capable of being implemented in semiconductor memory technology, a time delay of said time delay apparatus determined in response to a plurality of control signals, comprising: a plurality of time delay components coupled in a series configuration, each component including: a time delay circuit; a gate means responsive to a first state of a control signal for coupling an input terminal of said time delay circuit to an input signal, a second state of said control signal causing said input signal to by-pass said time delay circuit; a counter unit coupled to an output terminal of said programmable time delay apparatus; and an inverting amplifier coupled to said output terminal of said programmable time delay apparatus and to an input terminal of said programmable time delay apparatus.
Claim 2
Dependent Claim
132 words
A programmable time delay apparatus capable of being implemented in semiconductor memory technology, a time delay of said time delay apparatus determined in response to a plurality of control signals, comprising: a plurality of time delay components coupled in a series configuration, each component including: a time delay circuit; a gate means responsive to a first state of a control signal for coupling an input terminal of said time delay circuit to an input signal, a second state of said control signal causing said input signal to by-pass said time delay circuit; a counter unit coupled to an output terminal of said programmable time delay apparatus; and an inverting amplifier coupled to said output terminal of said programmable time delay apparatus and to an input terminal of said programmable time delay apparatus.