Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path

Claim 2

A non-volatile memory, comprising: a plurality of non-volatile memory cells; address decode logic; a plurality of access lines connecting said address decode logic to said memory cells; and a plurality of electrical latches connected to at least a subset of said access lines; wherein one of said latches is configured to hold a first word line at a write voltage while another of said latches is configured to hold a second word line at a read voltage.

Claim 3

A non-volatile memory according to claim 1, wherein: said memory cells are organized into at least two sectors.

Claim 4

A non-volatile memory according to claim 1, wherein: said memory cells are organized into at least two banks.

Claim 5

A non-volatile memory according to claim 1, wherein: said memory cells are flash memory cells.

Claim 6

A non-volatile memory according to claim 1, wherein: said latches are at least partially enabled by a read operation signal and a write operation signal such that said one of said latches holds a first word line at a read voltage while said another of said latches holds a second word line at a write voltage.

Claim 7

A non-volatile memory according to claim 1, further including: an address transition detector communicating a first load signal to said plurality of electrical latches causing a first selected latch of said plurality of electrical latches to hold a first selected word line at a first voltage during a first time period.

Claim 8

A non-volatile memory according to claim 6, further including: a control circuit in communication with said address transition detector and said address decode logic, said control circuit generating a first address and a second load signal, said second load signal being communicated to said plurality of electrical latches causing a second selected latch of said plurality of electrical latches to hold a second selected word line at a second voltage during a second time period, said first time period capable of at least partially overlapping with said second time period.

Claim 9

A non-volatile memory according to claim 7, further including: a selection circuit receiving said first address and a second address, said second address originating from a source external to said non-volatile memory, said selection circuit selectively communicates either said first address or said second address to said address decode logic.

Claim 10

A non-volatile memory according to claim 1, wherein: said address decode logic includes word line decode logic; said access lines include word lines connecting said word line decode logic to said memory cells; and said electrical latches are connected to said word lines.

Claim 11

A non-volatile memory according to claim 9, further including: an address transition detector communicating a first load signal to said electrical latches.

Claim 12

A non-volatile memory according to claim 1, wherein: said address decode logic includes word line decode logic and bit line decode logic; said access lines includes word lines connecting said word line decode logic to said memory cells and bit lines connecting said bit line decode logic to said memory cells; and said electrical latches are connected to said word lines.

Claim 13

A non-volatile memory according to claim 1, wherein: said address decode logic includes word line decode logic and bit line decode logic; said access lines include word lines connecting said word line decode logic to said memory cells and bit lines connecting said bit line decode logic to said memory cells; and said electrical latches are connected to said word lines and said bit lines.

Claim 14

A non-volatile memory according to claim 1, wherein: said memory cells are flash memory cells; said flash memory cells are organized into at least a first bank of memory cells and a second bank of memory cells; said address decode logic includes word line decode logic, first bit line decode logic and second bit line decode logic; said access lines include word lines connecting said word line decode logic to said first bank of memory cells and said second bank of memory cells, a first set of bit lines connecting said first bit line decode logic to said first bank of memory cells and a second set of bit lines connecting said second bit line decode logic to said second bank of memory cells; and said electrical latches are connected to said word lines.

Claim 15

A non-volatile memory according to claim 13, further including: an address transition detector communicating a first load signal to said plurality of electrical latches causing a first selected latch of said plurality of electrical latches to hold a first selected word line at a first voltage during a first time period; a control circuit in communication with said address transition detector and said address decode logic, said control circuit generating a first address and a second load signal, said second load signal being communicated to said plurality of electrical latches causing a second selected latch of said plurality of electrical latches to hold a second selected word line at a second voltage during a second time period, said first time period and said second time period capable of at least partially overlapping; and a selection circuit receiving said first address and a second address, said second address originating from a source external to said non-volatile memory, said selection circuit selectively communicates either said first address or said second address to said address decode logic.

Claim 16

A non-volatile memory according to claim 14, further including: a sense amplifier in communication with said memory cells.

Claim 17

A non-volatile memory according to claim 14, further including: a first sense amplifier in communication with said first bank of memory cells; and a second sense amplifier in communication with said second bank of memory cells.

Claim 18

A non-volatile memory according to claim 4, wherein: said flash memory cells are organized into at least two sets of memory cells; said address decode logic includes word line decode logic, first bit line decode logic and second bit line decode logic; said access lines includes word lines connecting said word line decode logic to said memory cells, a first set of bit lines connecting said first bit line decode logic to said memory cells and a second set of bit lines connecting said second bit line decode logic to said memory cells; and said electrical latches are connected to said word lines.

Claim 19

A non-volatile memory according to claim 17, further including: at least one sense amplifier in communication with said memory cells.

Claim 20

A non-volatile memory according to claim 17, further including: an address transition detector communicating a first load signal to said plurality of electrical latches causing a first selected latch of said plurality of electrical latches to hold a first selected word line at a first voltage during a first time period; a control circuit in communication with said address transition detector and said address decode logic, said control circuit generating a first address and a second load signal, said second load signal being communicated to said plurality of electrical latches causing a second selected latch of said plurality of electrical latches to hold a second selected word line at a second voltage during a second time period, said first time period and said second time period capable of at least partially overlapping; and a selection circuit receiving said first address and a second address, said second address originating from a source external to said non-volatile memory, said selection circuit selectively communicates either said first address or said second address to said address decode logic.

Claim 21

A flash memory device, comprising: a plurality of flash memory cells; only one word decode path including word decode logic, word lines, and electrical latches, said word lines connected to said word decode logic and said flash memory cells, said electrical latches connected to said word lines such that more than one word line can be driven at different voltage levels during a single time period; and at least a first bit decode path including bit decode logic and bit lines connected to said bit decode logic and said flash memory cells.

Claim 22

A flash memory device, comprising: a plurality of flash memory cells; only one word decode path including word decode logic, word lines, and electrical latches, said word lines connected to said word decode logic and said flash memory cells, said electrical latches connected to said word lines such that more than one word line can be driven at different voltage levels during a single time period; and at least a first bit decode path including bit decode logic and bit lines connected to said bit decode logic and said flash memory cells.

Claim 23

A flash memory device according to claim 20, further including: an address transition detector communicating a first load signal to said electrical latches causing a first selected latch to hold a first selected word line at a first voltage during a first time period; a control circuit in communication with said address transition detector and said address decode logic, said control circuit generating a first address and a second load signal, said second load signal being communicated to said electrical latches causing a second selected latch to hold a second selected word line at a second voltage during a second time period, said first time period and said second time period capable of at least partially overlapping; and a selection circuit receiving said first address and a second address, said second address originating from a source external to said flash memory device, said selection circuit selectively communicates either said first address or said second address to said address decode logic.

Claim 24

A flash memory device, comprising: a plurality of flash memory cells; an address transition detector; word line decode logic in communication with said address transition detector; word lines for connecting said word line decode logic to said flash memory cells; bit line decode logic in communication with said flash memory cells; and an electrical latch connected to at least one of said word lines and said word line decode logic; wherein said electrical latch is configured to allow at least one of said word lines to be held at a read voltage and another of said word lines to be held at a write voltage.

Claim 25

A flash memory device, comprising: a plurality of flash memory cells; an address transition detector; word line decode logic in communication with said address transition detector; word lines for connecting said word line decode logic to said flash memory cells; bit line decode logic in communication with said flash memory cells; and an electrical latch connected to at least one of said word lines and said word line decode logic; wherein said electrical latch is configured to allow at least one of said word lines to be held at a read voltage and another of said word lines to be held at a write voltage.

Claim 26

A non-volatile memory according to claim 22, wherein: said address transition detector generates a first load signal which is capable of actuating said latch.

Claim 27

A non-volatile memory according to claim 23, further including: a control circuit in communication with said address transition detector and said address decode logic, said control circuit generating a first address and a second load signal, said second load signal capable of actuating said latch; and a selection circuit receiving said first address and a second address, said second address originating from a source external to said flash memory device, said selection circuit selectively communicates either said first address or said second address to said word line decode logic.

Claim 28

A non-volatile memory, comprising: a plurality of flash memory cells; means for decoding an address to a plurality of word lines connected to said memory cells; first holding means for holding a first word line of said plurality of word lines at a write voltage, said first word line for accessing a first memory cell; and second holding means for holding a second word line of said plurality of word lines at a read voltage, said second word line for accessing a second memory cell, said second means capable of holding said second word line while said first means holds said first word line.

Claim 29

A non-volatile memory, comprising: a plurality of flash memory cells; means for decoding an address to a plurality of word lines connected to said memory cells; first holding means for holding a first word line of said plurality of word lines at a write voltage, said first word line for accessing a first memory cell; and second holding means for holding a second word line of said plurality of word lines at a read voltage, said second word line for accessing a second memory cell, said second means capable of holding said second word line while said first means holds said first word line.

Claim 30

A non-volatile memory according to claim 25, further including: means for performing a write process to said first memory cell; and means for reading from said second memory cell capable of reading from said second memory cell after said write process has begun and before said write process has completed.

Claim 31

A non-volatile memory according to claim 25, wherein: said first holding means and said second holding means include an electrical latch.

Claim 34

A method according to claim 28, wherein: said first access signal is supplied on a first word line; and said step c) holding latches said first access signal on said first word line.

Claim 35

A method according to claim 28, wherein: said step a) decoding includes receiving said first address and selecting a first word line.

Claim 36

A method according to claim 28, wherein: said step b) supplying includes driving a first word line.

Claim 37

A method according to claim 28, wherein: said step d) writing includes erasing data from said first memory cell.

Claim 38

A method according to claim 28, wherein: said step d) writing includes programming said first memory cell.

Claim 41

A method according to claim 34, wherein: said first and second memory cells are flash memory cells.

Claim 42

A method according to claim 34, wherein: said write process includes erasing multiple flash memory cells.

Claim 43

A method according to claim 34, wherein: said step of holding said first access line being performed during a first time period; and said step of holding said second access line being performed during a second time period, said first time period capable of at least partially overlapping with said second time period.

Claim 44

A method according to claim 34, further including the step of: detecting a first address transition; generating a first signal indicating said first address transition; communicating said first signal to a first latch, said first latch performing said step of holding said first access line; detecting a second address transition; generating a second signal indicating said second address transition; and communicating said second signal to a second latch, said second latch performing said step of holding said second access line.

Claim 45

A method according to claim 38, wherein: said step of communicating said first signal is performed at a different time than said step of communicating said second signal.

Claim 46

A flash memory, comprising: a plurality of flash memory cells; and means for writing to a first set of said flash memory cells while reading a second set of said flash memory cells; wherein said means for writing includes means for holding, at least partially during a same time period, a first word line at a write voltage and a second word line at a read voltage.

Claim 47

A flash memory, comprising: a plurality of flash memory cells; and means for writing to a first set of said flash memory cells while reading a second set of said flash memory cells; wherein said means for writing includes means for holding, at least partially during a same time period, a first word line at a write voltage and a second word line at a read voltage.