Patent US5841293A successfully refreshed from Google Patents.
US5841293A
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US
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Method and apparatus for screening integrated circuit chips for latch-up sensitivity
Assignee: International Business Machines Corp
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Filing: 1995-12-22
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Granted: 1998-11-24
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Expires: 2015-12-22
Abstract
Abstract Integrated circuit chips are screened for susceptibility to latch-up by first applying power and ground to the chips to be tested while limiting current flow to a non-destructive compliance value. Next, the chips are irradiated with a pulse of radiation having an energy dose calibrated to trigger latch-up in latch-up sensitive chips. Upon termination of the radiation, the current is detected. Chips having current persisting at the compliance value are indicated as failing. The current in passing chips returns approximately to the original standby current value. In the preferred embodiment, the radiation is visible light and the radiation energy dose is selected to cause a percentage of chips to latch-up approximating the percentage of failures expected at burn-in.
Inventors
- 👤 James Marc Leas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:55
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/282; G01R31/2831
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
111 words
A method of screening a semiconductor chip for susceptibility to latch-up, the method comprising the steps of: a) applying power and ground voltage to the chip; b) limiting current flow in the chip to a compliance value; c) irradiating the powered-up chip with a pulse of radiation, said radiation providing an energy dose to the chip calibrated to trigger latch-up in a latch-up sensitive chip so as to distinguish passing and failing chips, wherein, following said radiation pulse, current in a failing chip remains approximately at said compliance value; d) detecting current in the chip after said irradiating step (c) is complete; and e) indicating the chip as passing or failing.
Claim 2
Independent Claim
111 words
A method of screening a semiconductor chip for susceptibility to latch-up, the method comprising the steps of: a) applying power and ground voltage to the chip; b) limiting current flow in the chip to a compliance value; c) irradiating the powered-up chip with a pulse of radiation, said radiation providing an energy dose to the chip calibrated to trigger latch-up in a latch-up sensitive chip so as to distinguish passing and failing chips, wherein, following said radiation pulse, current in a failing chip remains approximately at said compliance value; d) detecting current in the chip after said irradiating step (c) is complete; and e) indicating the chip as passing or failing.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein said detecting step (d) includes measuring current flow in the chip.
Claim 4
Dependent Claim
27 words
The method of claim 1, wherein said detecting step (d) includes determining whether current flow in the chip is equal to or greater than a specified value.
Claim 5
Dependent Claim
10 words
The method of claim 1, said radiation being visible light.
Claim 6
Dependent Claim
31 words
The method of claim 1, the chip having a standby current, said compliance value being significantly higher than the standby current and less than a current level that damages the chip.
Claim 7
Dependent Claim
23 words
The latch-up tester of claim 5, wherein, following said radiation pulse, current in a passing chip returns approximately to the standby current level.
Claim 8
Dependent Claim
21 words
The method of claim 1, wherein in said irradiating step (c) said dose being set so a percentage of chips fail.
Claim 9
Dependent Claim
25 words
The method of claim 7, wherein in said irradiating step (c) said percentage being approximately equal to the percentage of chips that fail in burn-in.
Claim 10
Dependent Claim
118 words
A tester for testing a semiconductor chip for susceptibility to latch-up, the tester comprising: a power supply for supplying power and ground voltage to the chip for test; a compliance current limiter set to limit current to a compliance value; an irradiation source capable of irradiating the powered-up chip with a pulse of radiation, said radiation for providing an energy dose to the chip calibrated to trigger latch-up in a latch-up sensitive chip so as to distinguish passing and failing chips, wherein, following said radiation pulse, current in a failing chip remains approximately at said compliance value; a current detector; and an indicator to sort the chip as passing or failing after said pulse of radiation is complete.
Claim 11
Dependent Claim
118 words
A tester for testing a semiconductor chip for susceptibility to latch-up, the tester comprising: a power supply for supplying power and ground voltage to the chip for test; a compliance current limiter set to limit current to a compliance value; an irradiation source capable of irradiating the powered-up chip with a pulse of radiation, said radiation for providing an energy dose to the chip calibrated to trigger latch-up in a latch-up sensitive chip so as to distinguish passing and failing chips, wherein, following said radiation pulse, current in a failing chip remains approximately at said compliance value; a current detector; and an indicator to sort the chip as passing or failing after said pulse of radiation is complete.
Claim 12
Dependent Claim
15 words
The latch-up tester of claim 9, wherein said detector measures current flow in the chip.
Claim 13
Dependent Claim
25 words
The latch-up tester of claim 10, wherein said detector determines whether current flow in the chip is equal to or greater than a specified value.
Claim 14
Dependent Claim
11 words
The latch-up tester of claim 9, said radiation being visible light.
Claim 15
Dependent Claim
32 words
The latch-up tester of claim 9, the chip having a standby current, said compliance value being significantly higher than the standby current and less than a current level that damages the chip.
Claim 16
Dependent Claim
23 words
The latch-up tester of claim 13, wherein, following said radiation pulse, current in a passing chip returns approximately to the standby current level.
Claim 17
Dependent Claim
16 words
The latch-up tester of claim 9, said dose being set so a percentage of chips fail.
Claim 18
Dependent Claim
20 words
The latch-up tester of claim 15, said percentage being approximately equal to the percentage of chips that fail in burn-in.
Claim 19
Dependent Claim
19 words
The method of claim 1, wherein in said irradiating step (c), irradiating said chip with exactly one said pulse.
Claim 20
Dependent Claim
18 words
The method of claim 1, wherein in said irradiating step (c), irradiating said entire chip with said pulse.
Claim 21
Dependent Claim
19 words
The latch-up tester of claim 1, said radiation source being capable of irradiating said entire chip with said pulse.
References Cited (Backward Citations)
US4786865A
Cited
US5396169A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |