Field effect transistor and CMOS element having dopant exponentially graded in channel

Claim 2

A field effect transistor comprising: a channel region of a first conductivity type formed in a superficial semiconductor layer overlying an electrically insulating substrate; a source region and a drain region of a second conductivity type different from said first conductivity type, said source and drain regions being disposed with said channel region therebetween; a highly doped portion provided in said channel region at least in a section adjacent to said source region, said highly doped portion having a doping profile N(x) formed so that a concentration of impurities of said first conductivity type is substantially monotonically lowered toward a center portion of said channel region; and a gate electrode insulated from said channel region by an electrically insulating layer, wherein said doping profile N(x) substantially conforms to the expression: N(x)=N.sub.0 +N.sub.B0 ·exp -(η·x).sup.g)! where N 0 is a minimum doping level, N B0 is a maximum doping level, x is a displacement in μm from said highly doped portion toward said center portion of said channel region, g is a doping profile sharpness, and η is a doping profile gradient coefficient.

Claim 3

The field effect transistor according to claim 1, wherein said doping profile provides a parasitic transistor current gain of said field effect transistor that is less than a parasitic transistor current gain provided by a uniform doping profile.

Claim 4

The field effect transistor according to claim 1, wherein said doping profile is set so that said channel region is fully depleted when forming an inversion layer.

Claim 5

The field effect transistor according to claim 3, wherein a thickness of said superficial semiconductor layer is between 30 nm and 100 nm.

Claim 6

The field effect transistor according to claim 1, wherein when said doping profile gradient coefficient, η is between 8 and 20 ημm -1 .

Claim 7

The field effect transistor according to claim 1, wherein said sharpness g is 1, and said gradient coefficient η is between 16 μm -1 and 18 μm -1 .

Claim 8

The field effect transistor according to claim 1, wherein said sharpness g is between 4 and 8, and said gradient coefficient η is between 8 μm -1 and 15 μm -1 .

Claim 9

The field effect transistor according to claim 1, wherein said doping profile forms a gaussian profile, and a gradient of said doping profile of said first conductivity type from said highly doped portion toward said center portion of said channel region is between 3×10 22 /cm 4 and 8×10 22 /cm 4 .

Claim 10

The field effect transistor according to claim 8, wherein said impurities of said first conductivity type are boron.

Claim 11

The field effect transistor according to claim 1, wherein said highly doped portion is provided in said channel region on both sides thereof, and adjacent to said source region and said drain region.

Claim 12

The field effect transistor according to claim 1, wherein at least one of said source and drain regions adjacent to said highly doped portion includes: a first region adjacent to said highly doped portion; and a second region in which a doping level of impurities of said second conductivity type is higher than in said first region.

Claim 13

The field effect transistor according to claim 1, wherein at least a part of said source and drain regions and said gate electrode is salicided.

Claim 14

A complementary metal oxide semiconductor element with a complementary metal oxide semiconductor structure comprising: a first field effect transistor which is a field effect transistor defined in claim 1, wherein said first conductivity type is N type; and a second field effect transistor which is a field effect transistor defined in claim 1, wherein said first conductivity type is P type.

Claim 15

The field effect transistor according to claim 1, wherein said doping profile sharpness g is 2, and said doping profile gradient coefficient η is around 15 (μm -1 ).

Claim 16

A field effect comprising: a channel region of a first conductivity type formed in a superficial semiconductor layer overlying an electrically insulating substrate; a source region and a drain region of a second conductivity type different from said first conductivity type, said source and drain regions being disposed with said channel region therebetween; a highly doped portion provided in said channel region at sections adjacent to said source and drain regions, said highly doped portion having a doping profile N(x) formed so that a concentration of impurities of said first conductivity type is substantially monotonically lowered toward a center portion of said channel region; and a gate electrode insulated from said channel region by an electrically insulating layer, wherein said doping profile N(x) substantially conforms to the expression: N(x)=N.sub.0 +N.sub.B0 ·{exp (- η·(x-L/2)!.sup.g)+exp (- η·(x+L/2)!.sup.g)} where N 0 is a minimum doping level, N B0 is a maximum doping level, L is a length in μm of said channel region, x is a displacement in μm from said center portion of said channel region toward said highly doped portion, g is a doping profile sharpness, and η is a doping profile gradient coefficient.

Claim 17

A field effect comprising: a channel region of a first conductivity type formed in a superficial semiconductor layer overlying an electrically insulating substrate; a source region and a drain region of a second conductivity type different from said first conductivity type, said source and drain regions being disposed with said channel region therebetween; a highly doped portion provided in said channel region at sections adjacent to said source and drain regions, said highly doped portion having a doping profile N(x) formed so that a concentration of impurities of said first conductivity type is substantially monotonically lowered toward a center portion of said channel region; and a gate electrode insulated from said channel region by an electrically insulating layer, wherein said doping profile N(x) substantially conforms to the expression: N(x)=N.sub.0 +N.sub.B0 ·{exp (- η·(x-L/2)!.sup.g)+exp (- η·(x+L/2)!.sup.g)} where N 0 is a minimum doping level, N B0 is a maximum doping level, L is a length in μm of said channel region, x is a displacement in μm from said center portion of said channel region toward said highly doped portion, g is a doping profile sharpness, and η is a doping profile gradient coefficient.

Claim 18

The field effect transistor according to claim 15, wherein said doping profile gradient coefficient η is set between 8 μm -1 and 20 μm -1 .

Claim 19

The field effect transistor according to claim 15, wherein said doping profile is set so that said channel region is fully depleted when forming an inversion layer.

Claim 20

The field effect transistor according to claim 17, wherein a thickness of said superficial semiconductor layer is between 30 nm and 100 nm.

Claim 21

The field effect transistor according to claim 15, wherein said sharpness g is 1, and said gradient coefficient η is between 16 μm -1 and 18 μm -1 .

Claim 22

The field effect transistor according to claim 15, wherein said sharpness g is between 4 and 8, and said gradient coefficient η is between 8 μm -1 and 15 μm -1 .

Claim 23

The field effect transistor according to claim 15, wherein said doping profile sharpness g is 2, and said doping profile gradient coefficient η is approximately 15 μm -1 .

Claim 24

The field effect transistor according to claim 21, wherein said impurities of said first conductivity type are boron.

Claim 25

The field effect transistor according to claim 15, wherein at least one of said source and drain regions adjacent to said highly doped portion includes: a first region adjacent to said highly doped portion; and a second region in which a doping level of impurities of said second conductivity type is higher than in said first region.

Claim 26

The field effect transistor according to claim 15, wherein at least a part of said source and drain regions and said gate electrode is salicided.

Claim 27

A complementary metal oxide semiconductor element with a complementary metal oxide semiconductor structure comprising: a first field effect transistor which is a field effect transistor as defined in claim 15, wherein said first conductivity type is N type; and a second field effect transistor which is a field effect transistor as defined in claim 15, wherein said first conductivity type is P type.