Patent US5838902A successfully refreshed from Google Patents.
US5838902A
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Copy protection circuit for a data in a memory
Assignee: SK Hynix Inc
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Filing: 1997-11-07
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Granted: 1998-11-17
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Expires: 2017-11-07
Abstract
Abstract An improved copy protection circuit of a data stored in a memory capable of advantageously protecting an illegal copying of a data stored in a memory such as a mask ROM (Read Only Memory) by storing a data in a security data store cell. The protection circuit includes a security data store circuit for storing a security data encoded in accordance with a chip enabling signal applied thereto, a switch circuit for outputting a switching signal controlled by the security data, and a data converting circuit for converting an input address by receiving the input address and the security data and for outputting the converted address or the input address to a X, Y-address buffer/decoder in accordance with an output of the switch circuit.
Inventors
- 👤 Jong Su Shin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:14
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1408; G11; G11C; G11C8/00; G11C8/20
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
111 words
A copy protection circuit for a data in a memory, comprising: a security data store circuit for storing a security data encoded in accordance with a chip enabling signal applied thereto; a program circuit coupled to said security data store circuit to program said security data store circuit; a switch circuit for outputting a switching signal controlled by the security data inputted through said program circuit; and a data converting circuit for converting an input address by receiving the input address and the security data and for outputting one of a converted address and the input address to an X, Y-address buffer/decoder in accordance with an output of the switch circuit.
Claim 2
Dependent Claim
111 words
A copy protection circuit for a data in a memory, comprising: a security data store circuit for storing a security data encoded in accordance with a chip enabling signal applied thereto; a program circuit coupled to said security data store circuit to program said security data store circuit; a switch circuit for outputting a switching signal controlled by the security data inputted through said program circuit; and a data converting circuit for converting an input address by receiving the input address and the security data and for outputting one of a converted address and the input address to an X, Y-address buffer/decoder in accordance with an output of the switch circuit.
Claim 3
Dependent Claim
17 words
The circuit of claim 1, wherein said security data store circuit is a programmable ROM(Read Only Memory).
Claim 4
Dependent Claim
28 words
The circuit of claim 2, wherein said programmable ROM consists of a predetermined number of memory cells which is the same as the number of the input address.
Claim 5
Dependent Claim
46 words
The circuit of claim 3, wherein each of said memory cell includes a first transistor controlled in accordance with a chip enabling signal applied thereto, and a fuse connected to an output terminal the transistor and fused in accordance with a chip enabling signal applied thereto.
Claim 6
Dependent Claim
34 words
The circuit of claim 4, wherein said switch circuit includes a second transistor controlled in accordance with each security data and commonly connected with output terminals of the first transistor through the program circuit.
Claim 7
Dependent Claim
35 words
The circuit of claim 1, wherein said converted address is exclusively operated in response to an input address and a security data when an incorrect security data is inputted to said security data store circuit.
Claim 8
Dependent Claim
32 words
The circuit of claim 1, wherein said data converting circuit includes a transfer cable for transferring the converted address and the input address in accordance with an output of the switch circuit.
References Cited (Backward Citations)
US5446864A
Cited
US5499295A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |