Patent US5838627A successfully refreshed from Google Patents.
US5838627A
Expired / Lapsed
US
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Arrangement of power supply and data input/output pads in semiconductor memory device
Assignee: VACHELLIA LLC
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Filing: 1996-12-16
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Granted: 1998-11-17
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Expires: 2016-12-16
Abstract
Abstract Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supply voltage to data input/output pad portions, and power supply pad transmits the power supply voltage to data input/output pad portions. Power supply pad for peripheral circuitry is arranged in the center portion of the center region. A multibit test circuit is provided for each memory block. A data input/output buffer operating stably at high speed is implemented in a large storage capacity memory device which in turn accommodates a multibit test mode.
Inventors
- 👤 Shigeki Tomishima
- 👤 Mikio Asakura
- 👤 Masaki Tsukude
- 👤 Kazutami Arimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:12
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G11C29/30; G11C29/34; G11C5/02; G11C5/025; G11C5/06; G11C5/063; G11C7/00; G11C7/10
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
186 words
A semiconductor memory device, comprising: a memory array divided into a plurality of memory blocks by a first region disposed along a first direction and a second region disposed along a second direction perpendicular to said first direction, said first region crossing said second region; a plurality of external signal receiving pads arranged in a crossing portion, the crossing portion being substantially a portion at which said first region crosses said second region, said plurality of external signal receiving pads receiving external signals, said plurality of memory blocks accessed by said external signals; a plurality of data output pads provided corresponding to said plurality of memory blocks respectively, said plurality of data output pads arranged in a region excluding said crossing portion in said first region, each of said plurality of data output pads being arranged adjacent to a corresponding one of said memory blocks; and a plurality of data output buffers provided corresponding to said plurality of data output pads respectively, each receiving data from a corresponding one of said memory blocks and outputting said data to a corresponding one of said data output pads.
Claim 2
Dependent Claim
186 words
A semiconductor memory device, comprising: a memory array divided into a plurality of memory blocks by a first region disposed along a first direction and a second region disposed along a second direction perpendicular to said first direction, said first region crossing said second region; a plurality of external signal receiving pads arranged in a crossing portion, the crossing portion being substantially a portion at which said first region crosses said second region, said plurality of external signal receiving pads receiving external signals, said plurality of memory blocks accessed by said external signals; a plurality of data output pads provided corresponding to said plurality of memory blocks respectively, said plurality of data output pads arranged in a region excluding said crossing portion in said first region, each of said plurality of data output pads being arranged adjacent to a corresponding one of said memory blocks; and a plurality of data output buffers provided corresponding to said plurality of data output pads respectively, each receiving data from a corresponding one of said memory blocks and outputting said data to a corresponding one of said data output pads.
Claim 3
Dependent Claim
117 words
A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in a first direction on either side of a first region perpendicular to said first direction; a plurality of data input/output means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in a prescribed region along said first direction, each said data input/output means including a buffer for transmitting and receiving data to and from the corresponding memory block and a pad connected to the buffer; and a plurality of peripheral buffer means arranged in the vicinity of the first region along said first direction for receiving an external signal for accessing said plurality of memory blocks.
Claim 4
Dependent Claim
117 words
A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in a first direction on either side of a first region perpendicular to said first direction; a plurality of data input/output means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in a prescribed region along said first direction, each said data input/output means including a buffer for transmitting and receiving data to and from the corresponding memory block and a pad connected to the buffer; and a plurality of peripheral buffer means arranged in the vicinity of the first region along said first direction for receiving an external signal for accessing said plurality of memory blocks.
Claim 5
Dependent Claim
26 words
The semiconductor memory device according to claim 2, wherein said prescribed region is a peripheral region in the first direction adjacent a periphery of said chip.
Claim 6
Dependent Claim
148 words
A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip; a plurality of data input/output means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in said center region, said data input/output means including a plurality of buffers for transmitting and receiving data to and from the corresponding memory blocks and a plurality of pads connected to the plurality of buffers; and a plurality of peripheral buffer means arranged in the vicinity of a center portion in said center region along said first direction for receiving an external signal for accessing said plurality of memory blocks, said plurality of data input/output buffer means being arranged in a region excluding the vicinity of said center portion.
Claim 7
Dependent Claim
148 words
A semiconductor memory device formed on a chip, comprising: a plurality of memory blocks arranged in alignment with each other in a first direction on both sides of a center region along said first direction on said chip; a plurality of data input/output means arranged corresponding to said plurality of memory blocks and adjacent to corresponding memory blocks in said center region, said data input/output means including a plurality of buffers for transmitting and receiving data to and from the corresponding memory blocks and a plurality of pads connected to the plurality of buffers; and a plurality of peripheral buffer means arranged in the vicinity of a center portion in said center region along said first direction for receiving an external signal for accessing said plurality of memory blocks, said plurality of data input/output buffer means being arranged in a region excluding the vicinity of said center portion.
Claim 8
Dependent Claim
88 words
The semiconductor memory device according to claim 4, wherein said plurality of data input/output buffer means are arranged in groups on one side and on another side with respect to a center portion in said center region along said first direction, and said semiconductor memory device further comprises a plurality of power pads arranged adjacent to each respective data input/output buffer means group on each of said one side and said other side for supplying a power source voltage only to an associated data input/output buffer means group.
Claim 9
Dependent Claim
37 words
The semiconductor memory device as recited in claim 5, wherein each of said plurality of power pads connects only a power interconnection line for supplying the power source voltage to an associated data input/output buffer means group.
Claim 10
Dependent Claim
67 words
The semiconductor memory device as recited in claim 5, wherein said plurality of data input/output buffer means are aligned on each of said one side and said other side of said center region, and said plurality of power pads are arranged in said center region so as to sandwich a corresponding data input/output buffer means group therebetween one each of said one side and said other side.
Claim 11
Dependent Claim
96 words
The semiconductor memory device as recited in claim 5, further comprising: a peripheral circuit arranged in the center portion between said one side and said other side of said center region, for receiving an external signal controlling an access to said plurality of memory blocks and for controlling the access to said plurality of memory blocks in response to the received external signal; and a peripheral power pad arranged exclusively for said peripheral circuit in said center portion for receiving externally applied power source voltage and supplying the received power source voltage to said peripheral circuit.
Claim 12
Dependent Claim
40 words
The semiconductor memory device as recited in claim 5, wherein each said power pad includes a power supply pad receiving an external power supply voltage for internal transmission, and a ground pad receiving an external ground potential for internal supply.
Claim 13
Dependent Claim
30 words
The semiconductor memory device as recited in claim 5, wherein each said power pad is arranged between data input/output buffer means in each said group of data input/output buffer means.
Claim 14
Dependent Claim
106 words
The semiconductor memory device as recited in claim 5, wherein data input/output buffer means in each said group of data input/output buffer means are arranged on at least two lines in the first direction, and said power pads in each group of data input/output buffer means includes power supply pads supplying a power supply voltage of said power source voltage arranged in alignment with data input/output buffer means on one line of said at least two lines, and ground pads supplying a ground voltage of said power source voltage arranged in alignment with data input/output buffer means on another line of said at least two lines.
Claim 15
Dependent Claim
85 words
The semiconductor memory device as recited in claim 5, wherein data input/output buffer means in each said group of data input/output buffer means are arranged on at least two lines, and said power source voltage comprises one power supply voltage and another power supply voltage and said power pads includes a power supply pad receiving the one power supply voltage for internal transmission and a ground pad receiving the other power supply voltage for internal transmission arranged in each of said at least two lines.
Claim 16
Dependent Claim
67 words
The semiconductor memory device as recited in claim 5, wherein said plurality of power pads include power supply pads supplying one power supply voltage and ground pads supplying another power supply voltage, and said plurality of power pads are aligned with said plurality of data input/output buffer means, and at least one data input/output buffer means is inserted between a power supply pad and a ground pad.
Claim 17
Dependent Claim
48 words
The semiconductor memory device as recited in claim 8, wherein each of said plurality of power pads receives a power supply voltage of a first voltage level, and said peripheral power pad receives a power supply voltage of a second voltage level different from said first voltage level.
Claim 18
Dependent Claim
28 words
The semiconductor memory device as recited in claim 5, wherein said plurality of power pads each connect an interconnection line supplying a power source voltage separate from others.
Claim 19
Dependent Claim
49 words
The semiconductor memory device according to claim 15, further comprising: a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.
Claim 20
Dependent Claim
61 words
The semiconductor memory device as recited in claim 6, wherein said plurality of data input/output buffer means are further grouped into subgroups of a predetermined number of data input/output buffer means in each of said groups, and each of said power pads connects an interconnection line supplying the power source voltage only to an associated subgroup of data input/output buffer means.
Claim 21
Dependent Claim
50 words
The semiconductor memory device according to claim 17, further comprising; a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission thereof to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.
Claim 22
Dependent Claim
81 words
The semiconductor memory device formed according to claim 2, wherein said plurality of data input/output buffer means are arranged in groups on one side and on another side with respect to said first region and, said semiconductor memory device further includes a plurality of power pads arranged adjacent to each respective data input/output buffer means group on each of said one side and said other side for supplying a power source voltage only to an associated data input/output buffer means group.
Claim 23
Dependent Claim
37 words
The semiconductor memory device as recited in claim 19, wherein each of said plurality of power pads connects only a power interconnection line for supplying the power source voltage to an associated data input/output buffer means group.
Claim 24
Dependent Claim
71 words
The semiconductor memory device as recited in claim 19, wherein said plurality of data input/output buffer means are aligned in said prescribed region on each of said one side and said other side of said first region, and said plurality of power pads are arranged in said prescribed region so as to sandwich a corresponding data input/output buffer means group therebetween on each of said one side and said other side.
Claim 25
Dependent Claim
90 words
The semiconductor memory device as recited in claim 19, further comprising: a peripheral circuit for receiving an external signal controlling an access to said plurality of memory blocks and for controlling the access to said plurality of memory blocks in response to the received external signal; and a peripheral power pad arranged exclusively for said peripheral circuit in a portion between said one side and said other side in said prescribed region for receiving externally applied power source voltage and supplying the received power source voltage to said peripheral circuit.
Claim 26
Dependent Claim
43 words
The semiconductor memory device as recited in claim 19, wherein each of said plurality of power pads includes a power supply pad receiving an external power supply voltage for internal transmission, and a ground pad receiving an external ground potential for internal supply.
Claim 27
Dependent Claim
34 words
The semiconductor memory device as recited in claim 19, wherein each of said plurality of power pads is arranged between data input/output buffer means in each of said groups of data input/output buffer means.
Claim 28
Dependent Claim
107 words
The semiconductor memory device as recited in claim 19, wherein data input/output buffer means in each of said groups of data input/output buffer means are arranged on at least two lines in the first direction, and said power pads in each group of data input/output buffer means include power supply pads supplying a power supply voltage of said power source voltage arranged in alignment with data input/output buffer means on one line of said at least two lines, and ground pads supplying a ground voltage of said power source voltage arranged in alignment with data input/output buffer means on another line of said at least two lines.
Claim 29
Dependent Claim
87 words
The semiconductor memory device as recited in claim 19, wherein data input/output buffer means in each said group of data input/output buffer means are arranged on at least two lines, and said power source voltage comprises one power supply voltage and another power supply voltage and said plurality of power pads include a power supply pad receiving the one power supply voltage for internal transmission and a ground pad receiving the other power supply voltage for internal transmission arranged in each of said at least two lines.
Claim 30
Dependent Claim
67 words
The semiconductor memory device as recited in claim 19, wherein said plurality of power pads include power supply pads supplying one power supply voltage and ground pads supplying another power supply voltage, and said plurality of power pads are aligned with said plurality of data input/output buffer means, and at least one data input/output buffer means is inserted between a power supply pad and a ground pad.
Claim 31
Dependent Claim
48 words
The semiconductor memory device as recited in claim 22, wherein each of said plurality of power pads receives a power supply voltage of a first voltage level, and said peripheral power pad receives a power supply voltage of a second voltage level different from said first voltage level.
Claim 32
Dependent Claim
28 words
The semiconductor memory device as recited in claim 19, wherein said plurality of power pads each connect an interconnection line supplying a power source voltage separate from others.
Claim 33
Dependent Claim
49 words
The semiconductor memory device according to claim 29, further comprising: a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.
Claim 34
Dependent Claim
61 words
The semiconductor memory device as recited in claim 20, wherein said plurality of data input/output buffer means are further grouped into subgroups of a predetermined number of data input/output buffer means in each of said groups, and each of said power pads connects an interconnection line supplying the power source voltage only to an associated subgroup of data input/output buffer means.
Claim 35
Dependent Claim
50 words
The semiconductor memory device according to claim 31, further comprising; a power bus coupled to an external terminal receiving an externally applied power source voltage for internal transmission thereof to the respective power pads and provided extending over said chip and at least one of said plurality of memory blocks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |