US5838192A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Junction field effect voltage reference
Assignee: Analog Devices Inc
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Filing: 1996-01-17
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Granted: 1998-11-17
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Expires: 2016-01-17
Abstract
Abstract A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.
Inventors
- 👤 Derek F. Bowers
- 👤 Larry C. Tippie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:36
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/247; G05F3/30
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
188 words
A JFET voltage reference which provides a positive output voltage, comprising: a pair of JFETs having source, drain and gate terminals, different channel doping densities which result in unequal pinchoff voltages, and equal channel width-to-length ratios, each JFET characterized by a source-drain current path between its respective source and drain terminals, an operational amplifier having inverting and noninverting inputs and an output, and a pair of equal current current sources, the source-drain current paths of said JFETs connected to opposite respective ones of said operational amplifier inputs and also to receive equal currents from said current sources and to establish respective current flow paths between said current sources and a ground reference through respective ones of said JFET source-drain current paths, said current source currents being sufficient to maintain said JFETs in saturation, and the gates of said JFETs connected across a resistor, said resistor being part of a resistance circuit that is connected to the operational amplifier output to reproduce the difference in pinchoff voltages between said JFETs across said resistor and to establish a voltage reference output as a function of the voltage across said resistor.
Claim 2
Dependent Claim
188 words
A JFET voltage reference which provides a positive output voltage, comprising: a pair of JFETs having source, drain and gate terminals, different channel doping densities which result in unequal pinchoff voltages, and equal channel width-to-length ratios, each JFET characterized by a source-drain current path between its respective source and drain terminals, an operational amplifier having inverting and noninverting inputs and an output, and a pair of equal current current sources, the source-drain current paths of said JFETs connected to opposite respective ones of said operational amplifier inputs and also to receive equal currents from said current sources and to establish respective current flow paths between said current sources and a ground reference through respective ones of said JFET source-drain current paths, said current source currents being sufficient to maintain said JFETs in saturation, and the gates of said JFETs connected across a resistor, said resistor being part of a resistance circuit that is connected to the operational amplifier output to reproduce the difference in pinchoff voltages between said JFETs across said resistor and to establish a voltage reference output as a function of the voltage across said resistor.
Claim 3
Dependent Claim
20 words
The voltage reference of claim 1, wherein said resistance circuit establishes said voltage reference output at said operational amplifier output.
Claim 4
Dependent Claim
12 words
The voltage reference of claim 1, wherein said JFETs are n-channel JFETs.
Claim 5
Dependent Claim
12 words
The voltage reference of claim 1, wherein said JFETs are p-channel JFETs.
Claim 6
Dependent Claim
15 words
The voltage reference of claim 1, wherein said JFETs have substantially equal gate doping levels.
Claim 7
Dependent Claim
188 words
A JFET voltage reference which provides a negative output, comprising: a pair of JFETs having source, drain and gate terminals, different channel doping densities which result in unequal pinchoff voltages, and equal channel width-to-length ratios, each JFET characterized by a source-drain current path between its respective source and drain terminals, an operational amplifier having inverting and noninverting inputs and an output, and a pair of equal current current sources, the source-drain current paths of said JFETs connected to opposite respective ones of said operational amplifier inputs and also to receive equal currents from said current sources and to establish respective current flow paths between said current sources and a negative voltage supply through respective ones of said JFET source-drain current paths, said current source currents being sufficient to maintain said JFETs in saturation, and the gates of said JFETs connected across a resistor, said resistor being part of a resistance circuit that is connected to the operational amplifier output to reproduce the difference in pinchoff voltages between said JFETs across said resistor and to establish a voltage reference output as a function of the voltage across said resistor.
Claim 8
Dependent Claim
188 words
A JFET voltage reference which provides a negative output, comprising: a pair of JFETs having source, drain and gate terminals, different channel doping densities which result in unequal pinchoff voltages, and equal channel width-to-length ratios, each JFET characterized by a source-drain current path between its respective source and drain terminals, an operational amplifier having inverting and noninverting inputs and an output, and a pair of equal current current sources, the source-drain current paths of said JFETs connected to opposite respective ones of said operational amplifier inputs and also to receive equal currents from said current sources and to establish respective current flow paths between said current sources and a negative voltage supply through respective ones of said JFET source-drain current paths, said current source currents being sufficient to maintain said JFETs in saturation, and the gates of said JFETs connected across a resistor, said resistor being part of a resistance circuit that is connected to the operational amplifier output to reproduce the difference in pinchoff voltages between said JFETs across said resistor and to establish a voltage reference output as a function of the voltage across said resistor.
Claim 9
Dependent Claim
20 words
The voltage reference of claim 6, wherein said resistance circuit establishes said voltage reference output at said operational amplifier output.
Claim 10
Dependent Claim
12 words
The voltage reference of claim 6, wherein said JFETs are n-channel JFETs.
Claim 11
Dependent Claim
12 words
The voltage reference of claim 6, wherein said JFETs are p-channel JFETs.
Claim 12
Dependent Claim
15 words
The voltage reference of claim 6, wherein said JFETs have substantially equal gate doping levels.
References Cited (Backward Citations)
US4068134A
Cited
US4357571A
Cited
US4267501A
Cited
US4427903A
Cited
US4654578A
Cited
US4952821A
Cited
US5001484A
Cited
US5311115A
Cited
US5424663A
Cited
US5596265A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
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