Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses

Abstract

Abstract A central processing unit (CPU) of a computer and a method for reducing memory latencies in a computer memory hierarchy are described. The CPU includes an external cache controller and a primary memory controller. An instruction buffer in the primary memory controller stores an address from a primary memory page corresponding to a previous address request. A comparator circuit of the primary memory controller is used to compare a present address request corresponding to an instruction cache miss signal to the address stored in the instruction buffer. If an instruction buffer hit is achieved, memory latencies associated with the external cache controller and the primary memory controller are avoided. If an instruction buffer miss is experienced, the primary memory controller, under predetermined conditions, stores, in the instruction buffer, an address following an address corresponding to data from a primary memory page specified by the present address request. This operation frequently results in the instruction buffer storing early, i.e., prefetching, an address request that may be subsequently called by a computer program. When this is achieved, an address request may be rapidly retrieved without incurring the memory latency overhead of the external cache controller and the primary memory controller. The predetermined conditions may include that the address request corresponds to an instruction, and that an address follow signal and a memory controller free signal are generated. In alternative embodiments, the instruction buffer may be checked for a miss before or after the external cache is checked for a cache miss.

Inventors

• 👤 Rajasekhar Cherabuddi

Bibliographic Details