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US5835752A
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PCI interface synchronization
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-10-18
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Granted: 1998-11-10
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Expires: 2016-10-18
Abstract
Abstract A PCI interface includes a PCI core that operates at the PCI bus frequency and glue logic which provides an interface to a higher frequency clock domain. The glue logic includes FIFO buffers for addresses and data coming from or going to the PCI bus, and synchronizers for control signals coming from or going to the PCI core. In one embodiment, a novel synchronizer includes three flip-flops at least two of which are JK flip-flops.
Inventors
- 👤 Kevin Chiang
- 👤 Amjad Z. Qureshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:27
CPC Classifications
H; H03; H03K; H03K19/00; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
241 words
A bus interface comprising a first bus control circuit which operates at a first frequency of a first bus and implements a bus protocol for communications on the first bus; a second bus control circuit which operates at a second frequency of a second bus and implements a bus protocol for communications on the second bus, wherein the second frequency is independent of the first frequency; a first first-in-first-out buffer coupled between the first and second busses; and a synchronizer coupled between the first bus control circuit and the second bus control circuit, wherein the synchronizer comprises: a first JK flip-flop having a clock terminal coupled to receive a second clock signal, a first input terminal coupled to receive an input signal which is synchronized with the second clock signal; a second JK flip-flop having a clock terminal coupled to receive the second clock signal, a first input terminal coupled to a voltage source, an output terminal coupled to a second input terminal of the first JK flip-flop; a third flip-flop having a clock terminal coupled to a first clock signal and an output terminal coupled to a second input terminal of the second JK flip-flop; and a logic gate having a first input terminal coupled to an output terminal of the first JK flip-flop, a second input terminal coupled to the output terminal of the third flip-flop, and an output terminal coupled to an input terminal of the third flip-flop.
Claim 2
Dependent Claim
241 words
A bus interface comprising a first bus control circuit which operates at a first frequency of a first bus and implements a bus protocol for communications on the first bus; a second bus control circuit which operates at a second frequency of a second bus and implements a bus protocol for communications on the second bus, wherein the second frequency is independent of the first frequency; a first first-in-first-out buffer coupled between the first and second busses; and a synchronizer coupled between the first bus control circuit and the second bus control circuit, wherein the synchronizer comprises: a first JK flip-flop having a clock terminal coupled to receive a second clock signal, a first input terminal coupled to receive an input signal which is synchronized with the second clock signal; a second JK flip-flop having a clock terminal coupled to receive the second clock signal, a first input terminal coupled to a voltage source, an output terminal coupled to a second input terminal of the first JK flip-flop; a third flip-flop having a clock terminal coupled to a first clock signal and an output terminal coupled to a second input terminal of the second JK flip-flop; and a logic gate having a first input terminal coupled to an output terminal of the first JK flip-flop, a second input terminal coupled to the output terminal of the third flip-flop, and an output terminal coupled to an input terminal of the third flip-flop.
Claim 3
Dependent Claim
32 words
The bus interface of claim 1, wherein the first bus operates at the frequency of the first clock signal, and the second bus operates at the frequency of the second clock signal.
Claim 4
Dependent Claim
14 words
The bus interface of claim 2, wherein the first bus is a PCI bus.
Claim 5
Dependent Claim
147 words
A synchronizer comprising: a first JK flip-flop having a clock terminal coupled to receive a first clock signal, a first input terminal coupled to receive an input signal which is synchronized with the first clock signal; a second JK flip-flop having a clock terminal coupled to receive the first clock signal, a first input terminal coupled to a voltage source, an output terminal coupled to a second input terminal of the first JK flip-flop; a third flip-flop having a clock terminal coupled to a second clock signal and an output terminal coupled to a second input terminal of the second JK flip-flop; and a logic gate having a first input terminal coupled to an output terminal of the first JK flip-flop, a second input terminal coupled to the output terminal of the third flip-flop, and an output terminal coupled to an input terminal of the third flip-flop.
Claim 6
Dependent Claim
147 words
A synchronizer comprising: a first JK flip-flop having a clock terminal coupled to receive a first clock signal, a first input terminal coupled to receive an input signal which is synchronized with the first clock signal; a second JK flip-flop having a clock terminal coupled to receive the first clock signal, a first input terminal coupled to a voltage source, an output terminal coupled to a second input terminal of the first JK flip-flop; a third flip-flop having a clock terminal coupled to a second clock signal and an output terminal coupled to a second input terminal of the second JK flip-flop; and a logic gate having a first input terminal coupled to an output terminal of the first JK flip-flop, a second input terminal coupled to the output terminal of the third flip-flop, and an output terminal coupled to an input terminal of the third flip-flop.
Claim 7
Dependent Claim
13 words
The synchronizer of claim 4, wherein the third flip-flop is a D flip-flop.
Claim 8
Dependent Claim
13 words
The synchronizer of claim 4, wherein the logic gate is a NAND gate.
Claim 9
Dependent Claim
23 words
The synchronizer of claim 4, wherein the second JK flip-flop has a second input terminal which is coupled to a constant voltage source.
Claim 10
Dependent Claim
63 words
The synchronizer of claim 7, wherein the second input terminal is a reset terminal to which the constant voltage source applies a constant voltage, and in response to an output voltage on the output terminal of the second JK flip-flop being high, an edge of the first clock signal causes the second JK flip-flop to reset the output voltage to a low level.
Claim 11
Dependent Claim
34 words
The synchronizer of claim 7, wherein the first input terminals of the first and second JK flip-flop are set terminals, and the second input terminals of the first second JK flip-flops are reset terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |