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Patent US5835733A successfully refreshed from Google Patents.
US5835733A
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Method and apparatus for implementing a single DMA controller to perform DMA operations for devices on multiple buses in docking stations, notebook and desktop computer system
Assignee: Texas Instruments Inc
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Filing: 1994-12-22
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Granted: 1998-11-10
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Expires: 2014-12-22
Abstract
Abstract A computer system (6,7) includes first and second I/O circuits (932, 934), 51, 97 first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), 51, 97 a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an related information between the DMA controller and a requesting device in the docking station. Other devices, systems and methods are also disclosed.
Inventors
- 👤 James J. Walsh
- 👤 Joseph Joe
- 👤 Robert W. Milhaupt
- 👤 James Bridgwater
- 👤 Kazumi Haijima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:55
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
162 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, and a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, comprising the steps of: operating said DMA controller to perform a read of data from said memory via said first bus interface circuit and said third bus, a temporary store of said data in a register associated with said DMA controller, and a write of said data, via said third bus, to a write buffer associated with said second bus interface circuit; and operating said second bus interface circuit to perform an I/O write from said write buffer by initiating a pseudo memory read and an actual I/O write cycle.
Claim 2
Independent Claim
162 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, and a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, comprising the steps of: operating said DMA controller to perform a read of data from said memory via said first bus interface circuit and said third bus, a temporary store of said data in a register associated with said DMA controller, and a write of said data, via said third bus, to a write buffer associated with said second bus interface circuit; and operating said second bus interface circuit to perform an I/O write from said write buffer by initiating a pseudo memory read and an actual I/O write cycle.
Claim 3
Independent Claim
171 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit coupled between said DMA controller and said second bus interface circuit, comprising the steps of: operating said DMA controller to perform a memory read cycle, wherein if said memory read cycle is not granted by said memory or any device on said third bus sending a DMA current address via said communications circuit to said second bus interface circuit; and operating said second bus interface circuit, if said DMA current address is sent, to generate a memory read and I/O write cycle on the second bus utilizing said DMA current address supplied via said communications circuit.
Claim 4
Independent Claim
171 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit coupled between said DMA controller and said second bus interface circuit, comprising the steps of: operating said DMA controller to perform a memory read cycle, wherein if said memory read cycle is not granted by said memory or any device on said third bus sending a DMA current address via said communications circuit to said second bus interface circuit; and operating said second bus interface circuit, if said DMA current address is sent, to generate a memory read and I/O write cycle on the second bus utilizing said DMA current address supplied via said communications circuit.
Claim 5
Dependent Claim
14 words
The method of claim 2, wherein said communications circuit is a serial communications circuit.
Claim 6
Independent Claim
181 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit coupled between said DMA controller and said second bus interface circuit, comprising the steps of: operating said DMA controller to perform an I/O read cycle on said first bus, and a memory write cycle on said third bus, wherein if said memory write cycle is not granted by said memory or any device on said third bus sending a DMA current address via said communications circuit to said second bus interface circuit; and operating said second bus interface circuit, if said DMA current address is sent, to generate a memory write cycle on said second bus utilizing the DMA current address supplied via said communications circuit.
Claim 7
Independent Claim
181 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit coupled between said DMA controller and said second bus interface circuit, comprising the steps of: operating said DMA controller to perform an I/O read cycle on said first bus, and a memory write cycle on said third bus, wherein if said memory write cycle is not granted by said memory or any device on said third bus sending a DMA current address via said communications circuit to said second bus interface circuit; and operating said second bus interface circuit, if said DMA current address is sent, to generate a memory write cycle on said second bus utilizing the DMA current address supplied via said communications circuit.
Claim 8
Dependent Claim
14 words
The method of claim 4, wherein said communications circuit is a serial communications circuit.
Claim 9
Independent Claim
154 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit coupled between said DMA controller and said second bus interface circuit, comprising the steps of: sending a DMA request from said second bus via said communications circuit to said DMA controller; operating said DMA controller to send a DMA acknowledge via said communications circuit to said second bus interface circuit; and operating said second bus interface circuit to perform an I/O read cycle on said second bus, and a memory write cycle on both said second and third buses.
Claim 10
Independent Claim
154 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit coupled between said DMA controller and said second bus interface circuit, comprising the steps of: sending a DMA request from said second bus via said communications circuit to said DMA controller; operating said DMA controller to send a DMA acknowledge via said communications circuit to said second bus interface circuit; and operating said second bus interface circuit to perform an I/O read cycle on said second bus, and a memory write cycle on both said second and third buses.
Claim 11
Dependent Claim
14 words
The method of claim 6, wherein said communications circuit is a serial communications circuit.
Claim 12
Independent Claim
137 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit between said DMA controller and said second bus interface circuit, comprising the steps of: sending a master signal from said second bus via said communications circuit to said DMA controller; operating said DMA controller to sample the master signal during a DMA acknowledge; and transferring control of said third bus to said second bus interface circuit when a master signal is detected.
Claim 13
Independent Claim
137 words
A method of operating a computer system including first and second I/O circuits, first and second buses respectively coupled to said first and second I/O circuits, a memory, a third bus coupled to said memory, first and second bus interface circuits coupled between said third bus and said first and second buses respectively, a direct memory access (DMA) controller coupled to said first bus and to said first bus interface circuit, and a communications circuit between said DMA controller and said second bus interface circuit, comprising the steps of: sending a master signal from said second bus via said communications circuit to said DMA controller; operating said DMA controller to sample the master signal during a DMA acknowledge; and transferring control of said third bus to said second bus interface circuit when a master signal is detected.
Claim 14
Dependent Claim
14 words
The method of claim 8, wherein said communications circuit is a serial communications circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |