US5835704A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of testing system memory
Assignee: Intel Corp
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Filing: 1996-11-06
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Granted: 1998-11-10
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Expires: 2016-11-06
Abstract
Abstract A method of testing at least a selected portion of system memory for a microprocessor system is disclosed, the microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus. The method includes the steps of: writing at least a selected portion of system memory with a predetermined test pattern using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written.
Inventors
- 👤 Yan Li
- 👤 Mahesh Natu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:49
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G11C2029/0401; G11C2029/0407
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
130 words
A method of testing at least a selected portion of system memory for a microprocessor system, said microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus that will introduce a transfer bottleneck when performing uncached data value transfers, said method comprising the steps of: writing at least a selected portion of system memory with a predetermined test pattern over the system bus using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory over the system bus using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written.
Claim 2
Independent Claim
130 words
A method of testing at least a selected portion of system memory for a microprocessor system, said microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus that will introduce a transfer bottleneck when performing uncached data value transfers, said method comprising the steps of: writing at least a selected portion of system memory with a predetermined test pattern over the system bus using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory over the system bus using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written.
Claim 3
Dependent Claim
43 words
The method of claim 1, wherein the microprocessor includes a data cache adapted for performing burst mode operations, and wherein the step of writing using the burst mode capability of the microprocessor system comprises using the data cache to perform burst mode operations.
Claim 4
Dependent Claim
35 words
The method of claim 2, wherein the step of reading back values over the system bus using the burst mode capability of the microprocessor system comprises using the data cache to perform burst mode operations.
Claim 5
Dependent Claim
46 words
The method of claim 3, wherein the at least a selected portion of system memory comprises a data cache sized block of system memory; and further comprising performing the steps of writing, reading and comparing in data cache sized blocks over the remaining entire system memory.
Claim 6
Dependent Claim
30 words
The method of claim 1, and further comprising, prior to the writing, reading, and comparing steps, initializing the entire system memory using the burst mode capability of the microprocessor system.
Claim 7
Dependent Claim
36 words
The method of claim 4, and further compromising, after the step of performing, filling the entire system memory with a consistent data value over the system bus using the burst mode capability of the microprocessor system.
Claim 8
Independent Claim
174 words
A method of testing at least a selected portion of system memory for a microprocessor system, said microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus, said method comprising the steps of: writing at least a selected portion of system memory with a predetermined test pattern using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written; wherein the microprocessor system includes a write combining capability executed using a burst mode operation; wherein the step of writing using the burst mode capability of the microprocessor system comprises using the write combining capability of the microprocessor system; and wherein the step of reading using the burst mode capability of the microprocessor system comprises using the write combining capability of the microprocessor system.
Claim 9
Independent Claim
174 words
A method of testing at least a selected portion of system memory for a microprocessor system, said microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus, said method comprising the steps of: writing at least a selected portion of system memory with a predetermined test pattern using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written; wherein the microprocessor system includes a write combining capability executed using a burst mode operation; wherein the step of writing using the burst mode capability of the microprocessor system comprises using the write combining capability of the microprocessor system; and wherein the step of reading using the burst mode capability of the microprocessor system comprises using the write combining capability of the microprocessor system.
Claim 10
Dependent Claim
41 words
The method of claim 7, wherein the at least a selected portion of system memory comprises a memory line, and further comprising performing the steps of writing, reading and comparing a memory line at a time over the entire system memory.
Claim 11
Dependent Claim
30 words
The method of claim 8, and further comprising, prior to the writing, reading, and comparing steps, initializing the entire system memory using the burst mode capability of the microprocessor system.
Claim 12
Dependent Claim
32 words
The method of claim 8, and further comprising, after the step of performing, filling the entire system memory with a consistent data value using the burst mode capability of the microprocessor system.
Claim 13
Dependent Claim
100 words
A microprocessor system, including a microprocessor, having burst mode capability to transfer data values between the microprocessor and a system memory via a system bus that will introduce a transfer bottleneck when performing uncached data value transfers, said microprocessor system comprising a storage medium coupled thereto, said storage medium including machine-readable code stored thereon, wherein said machine-readable code is adapted, so that, when executed, the microprocessor system via the system bus uses burst mode operations to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of the system memory.
Claim 14
Dependent Claim
100 words
A microprocessor system, including a microprocessor, having burst mode capability to transfer data values between the microprocessor and a system memory via a system bus that will introduce a transfer bottleneck when performing uncached data value transfers, said microprocessor system comprising a storage medium coupled thereto, said storage medium including machine-readable code stored thereon, wherein said machine-readable code is adapted, so that, when executed, the microprocessor system via the system bus uses burst mode operations to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of the system memory.
Claim 15
Dependent Claim
69 words
The microprocessor system of claim 11, wherein said microprocessor includes a data cache adapted to perform burst mode operations via the system bus, and wherein said machine-readable code is further adapted so that, when executed, the microprocessor system uses the data cache to facilitate the transfer of data signal values between the microprocessor and the system memory during a test of at least a selected portion of system memory.
Claim 16
Dependent Claim
59 words
The microprocessor system of claim 11, wherein said machine-readable code is further adapted, so that, when executed, the microprocessor system further uses burst mode operations to transfer, via the system bus, data signal values between the microprocessor and the system memory during initialization of the entire system memory, before said test of at least a portion of system memory.
Claim 17
Dependent Claim
58 words
The microprocessor system of claim 11, wherein said machine-readable code is further adapted so that, when executed, the microprocessor system further uses burst mode operations to transfer, via the system bus, data signal values between the microprocessor and the system memory to fill the entire system memory, after said test of at least a portion of system memory.
Claim 18
Dependent Claim
141 words
A microprocessor system having burst mode capability to transfer data values between the microprocessor and a system memory via a system bus, said microprocessor system comprising a storage medium coupled thereto, said storage medium including machine-readable code stored thereon, wherein said machine-readable code is adapted, so that, when executed, the microprocessor system uses burst mode operations to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of the system memory; wherein said microprocessor includes a write combining capability executed using burst mode operations via the system bus; and wherein said machine-readable code is further adapted, so that, when executed, the microprocessor uses the write combining capability to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of system memory.
Claim 19
Dependent Claim
141 words
A microprocessor system having burst mode capability to transfer data values between the microprocessor and a system memory via a system bus, said microprocessor system comprising a storage medium coupled thereto, said storage medium including machine-readable code stored thereon, wherein said machine-readable code is adapted, so that, when executed, the microprocessor system uses burst mode operations to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of the system memory; wherein said microprocessor includes a write combining capability executed using burst mode operations via the system bus; and wherein said machine-readable code is further adapted, so that, when executed, the microprocessor uses the write combining capability to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of system memory.
Claim 20
Independent Claim
152 words
A method of testing at least a selected portion of system memory for a microprocessor system, said microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus, said method comprising the steps of: writing at least a selected portion of system memory with a predetermined test pattern using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written; wherein the microprocessor includes a data write back cache feature executed using a burst mode operation; and wherein the step of writing using the burst mode capability of the microprocessor comprises using the data write back cache feature of the microprocessor system.
Claim 21
Independent Claim
152 words
A method of testing at least a selected portion of system memory for a microprocessor system, said microprocessor system having burst mode capability to transfer data values between the microprocessor and the system memory via a system bus, said method comprising the steps of: writing at least a selected portion of system memory with a predetermined test pattern using the burst mode capability of the microprocessor system; reading back values from the at least a selected portion of system memory using the burst mode capability of the microprocessor system; and comparing the values read from the at least a selected portion of system memory with the predetermined test pattern written; wherein the microprocessor includes a data write back cache feature executed using a burst mode operation; and wherein the step of writing using the burst mode capability of the microprocessor comprises using the data write back cache feature of the microprocessor system.
Claim 22
Dependent Claim
144 words
A microprocessor system having burst mode capability to transfer data values between the microprocessor and a system memory via a system bus, said microprocessor system comprising a storage medium coupled thereto, said storage medium including machine-readable code stored thereon, wherein said machine-readable code is adapted, so that, when executed, the microprocessor system uses burst mode operations to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of the system memory; wherein said microprocessor includes a write back cache feature capability executed using burst mode operations via the system bus; and wherein said machine-readable code is further adapted, so that, when executed, the microprocessor uses the write back cache feature to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of system memory.
Claim 23
Dependent Claim
144 words
A microprocessor system having burst mode capability to transfer data values between the microprocessor and a system memory via a system bus, said microprocessor system comprising a storage medium coupled thereto, said storage medium including machine-readable code stored thereon, wherein said machine-readable code is adapted, so that, when executed, the microprocessor system uses burst mode operations to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of the system memory; wherein said microprocessor includes a write back cache feature capability executed using burst mode operations via the system bus; and wherein said machine-readable code is further adapted, so that, when executed, the microprocessor uses the write back cache feature to transfer data signal values between the microprocessor and the system memory during a test of at least a selected portion of system memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |