US5623633A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache-based computer system employing a snoop control circuit with write-back suppression
Assignee: Dell USA LP
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Filing: 1993-07-27
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Granted: 1997-04-22
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Expires: 2013-07-27
Abstract
Abstract A cache-based computer system is provided with a snoop control circuit that implements a write-back suppression technique. The snoop control circuit controls the write-back and invalidation of dirty data within a cache memory during a DMA write operation to maintain the integrity of data within the computer system. If an alternate bus master initiates a burst transfer cycle that does not encompass an entire line of valid data, the alternate bus master asserts a snoop write-back signal that causes the snoop control circuit to effectuate the write-back to system memory of a corresponding dirty line in the cache memory. Integrity of the data within the system is thereby maintained. On the other hand, if the alternate bus master initiates a burst transfer cycle that does encompass an entire line of valid data, the altemate bus master deasserts the snoop write-back signal. When the snoop write-back signal is deasserted, the snoop control circuit advantageously suppresses the write-back of the corresponding dirty data in the cache memory, thereby attaining reduced traffic on the system bus. Since the DMA operation involved the transfer of an entire line of valid data, the integrity of data is maintained even though the write-back of the dirty line was suppressed. As a result, the bandwidth of the computer system may be improved and the overall performance of the system may be enhanced.
Inventors
- 👤 Charles P. Zeller
- 👤 Darius D. Gaskins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:08
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835; G06F12/0877; G06F12/0886
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
241 words
A computer system comprising: a system bus; a cache memory coupled to said system bus; a microprocessor coupled to said cache memory; a system memory; a system memory controller coupled to said system bus and to said system memory for controlling the storage and retrieval of data within said system memory; an alternate bus master device coupled to said system bus, wherein said alternate bus master device is configured to assert a snoop write-back signal if a complete line of data is not being transferred to said system memory from said alternate bus master during a given burst write cycle and is configured to deassert said snoop write-back signal if a complete line of data is being transferred to said system memory from said alternate bus master device during said burst write cycle; and cache controller coupled to said cache memory and to said system bus for controlling the storage and retrieval of data within said cache memory, wherein said cache controller includes a snoop control circuit for controlling the write-back to said system memory of dirty data in the associated hit line stored within said cache memory if said snoop write-back signal is asserted when a DMA write operation occurs to said system memory from said alternate bus master device, and wherein said snoop control circuit inhibits the write-back of said dirty data to said system memory if said snoop write-back signal is deasserted when said DMA write operation occurs.
Claim 2
Dependent Claim
241 words
A computer system comprising: a system bus; a cache memory coupled to said system bus; a microprocessor coupled to said cache memory; a system memory; a system memory controller coupled to said system bus and to said system memory for controlling the storage and retrieval of data within said system memory; an alternate bus master device coupled to said system bus, wherein said alternate bus master device is configured to assert a snoop write-back signal if a complete line of data is not being transferred to said system memory from said alternate bus master during a given burst write cycle and is configured to deassert said snoop write-back signal if a complete line of data is being transferred to said system memory from said alternate bus master device during said burst write cycle; and cache controller coupled to said cache memory and to said system bus for controlling the storage and retrieval of data within said cache memory, wherein said cache controller includes a snoop control circuit for controlling the write-back to said system memory of dirty data in the associated hit line stored within said cache memory if said snoop write-back signal is asserted when a DMA write operation occurs to said system memory from said alternate bus master device, and wherein said snoop control circuit inhibits the write-back of said dirty data to said system memory if said snoop write-back signal is deasserted when said DMA write operation occurs.
Claim 3
Dependent Claim
18 words
The computer system as recited in claim 1 wherein said altemate bus master device is a DMA controller.
Claim 4
Dependent Claim
18 words
The computer system as recited in claim 1 wherein said alternate bus master device is a bus bridge.
Claim 5
Dependent Claim
29 words
The computer system as recited in claim 1 wherein said snoop control circuit invalidates a line of dirty data stored within said cache memory during said DMA write operation.
Claim 6
Dependent Claim
45 words
The computer system as recited in claim 1 wherein said write-back to said system memory of said dirty data stored within said cache memory occurs after selected data is transferred during said given burst cycle from said alternate bus master device to said system memory.
Claim 7
Dependent Claim
45 words
The computer system as recited in claim 1 wherein said write-back to said system memory of said dirty data stored within said cache memory occurs before selected data is transferred during said given burst cycle from said alternate bus master device to said system memory.
Claim 8
Dependent Claim
35 words
The computer system as recited in claim 1 wherein the write-back to said system memory of said dirty data stored within said cache memory is completed during a burst write cycle to said system memory.
Claim 9
Dependent Claim
170 words
A snoop control method for a cache-based computer system including a cache memory coupled to an alternate bus master and a system memory through a system bus, said method comprising the steps of: initiating, by said alternate bus master, a DMA write cycle to transfer data from said alternate bus master to said system memory; asserting, by said alternate bus master, a snoop write-back signal to a snoop control circuit within a cache controller coupled to said cache memory and said system bus if the DMA transfer does not encompass a complete cache line, and deasserting said snoop write-back signal if the DMA transfer encompass a complete cache line; invalidating, by said cache controller, an associated hit line within said cache memory; and writing back, by said cache controller, the associated hit line to a system memory controller coupled to said system memory if the snoop write-back signal is asserted, and not writing back the associated hit line to said system memory controller if the snoop write-back signal is deasserted.
Claim 10
Dependent Claim
170 words
A snoop control method for a cache-based computer system including a cache memory coupled to an alternate bus master and a system memory through a system bus, said method comprising the steps of: initiating, by said alternate bus master, a DMA write cycle to transfer data from said alternate bus master to said system memory; asserting, by said alternate bus master, a snoop write-back signal to a snoop control circuit within a cache controller coupled to said cache memory and said system bus if the DMA transfer does not encompass a complete cache line, and deasserting said snoop write-back signal if the DMA transfer encompass a complete cache line; invalidating, by said cache controller, an associated hit line within said cache memory; and writing back, by said cache controller, the associated hit line to a system memory controller coupled to said system memory if the snoop write-back signal is asserted, and not writing back the associated hit line to said system memory controller if the snoop write-back signal is deasserted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-21 | 2000-10-21 | 2001-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-21 | 2004-10-21 | 2005-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-21 | 2008-10-21 | 2009-04-22 | $7700.00 | Window Closed / Lapsed |