Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed

Claim 3

A system for controlling access to memory as in claim 1 in which the hardware means comprises: a look-aside buffer including a plurality of storage locations for virtual addresses and associated physical addresses, and a storage position in each storage location of the look aside buffer.

Claim 4

A system for controlling access to memory as in claim 1 in which the software means for initiating an instruction speculating that the address is memory or a memory mapped I/O device is a set of instructions for a host processor translated from a set of instructions for a target processor, the set of instructions including an indication of a speculation for each address used by the instruction.

Claim 5

A system for controlling access to memory as in claim 1 in which the hardware means comprises: a look-aside buffer including a plurality of storage locations for virtual addresses and associated physical addresses, and a storage position in each storage location of the look aside buffer; and in which the software means for initiating an instruction speculating that the address is memory or a memory mapped I/O device is a set of instructions for a host processor translated from a set of instructions for a target processor, the set of instructions including an indication of a speculation for each address used by the instruction.

Claim 6

A system for controlling access to memory as in claim 4 in which the means for comparing the speculation made with respect to the instruction with an indication of the hardware means comprises a hardware comparator for comparing the indication of a speculation for each address with a condition of a storage position in a storage location storing a matching address.

Claim 7

A memory controller for a microprocessor comprising: means to detect a failure of speculation on the physical nature of an address being affected by an operation, and means to recover from such a failure.

Claim 8

A memory controller for a microprocessor comprising: means to detect a failure of speculation on the physical nature of an address being affected by an operation, and means to recover from such a failure.

Claim 9

A memory controller as claimed in claim 6 in which the means to detect a failure of speculation on the physical nature of the address being affected by an operation comprises hardware means for storing an indication of the physical nature of the address being affected by an operation, and means for comparing a speculation on the physical nature of the address being affected by an operation and an indication of the physical nature of the address being affected by an operation stored by the hardware means.

Claim 10

A memory controller as claimed in claim 7 in which the means to recover from such failures comprises: means responsive to a failure of a comparison by the means for comparing a speculation on the physical nature of the address being affected by an operation and an indication of the physical nature of the address being affected by an operation for generating an exception, and means for responding to the exception.

Claim 11

A memory controller as claimed in claim 6 in which the means to detect a failure of speculation on the physical nature of the address being affected by an operation comprises hardware means for storing an indication of the physical nature of the address being affected by an operation, and means for comparing a speculation on the physical nature of the address being affected by an operation and an indication of the physical nature of the address being affected by an operation stored by the hardware means; and in which the means to recover from such failures comprises: means responsive to a failure of a comparison by the means for comparing a speculation on the physical nature of the address being affected by an operation and an indication of the physical nature of the address being affected by an operation for generating an exception, and means for responding to the exception.

Claim 12

A memory controller as claimed in claim 9 in which the means for responding to the exception comprises: means for recovering state of a computer utilizing the microprocessor, and means for accessing the address presuming the physical nature of the address being affected by an operation is different than the speculation.

Claim 13

A memory controller as claimed in claim 9 in which the means to recover from such a failure comprises: means for generating an exception in response to a failure of speculation on the physical nature of the address being affected by an operation, means for providing a process for recovering from an exception related to a failure of the speculation on the physical nature of the address being affected by an operation.

Claim 14

A memory control system for a computer comprising: main memory, memory-mapped input/output (I/O) devices, memory control software for causing commands to affect operations at particular addresses, a translation lookaside buffer including memory locations for storing virtual addresses which have been recently accessed and translations of those virtual addresses to physical addresses within the computer, at least one memory position for each memory location recording an indication whether the address is assumed to be memory or memory-mapped I/O, a comparator for detecting whether an instruction accessing a virtual address stored in the translation lookaside buffer presumes that the physical address is the same as the indication recorded for the physical address.

Claim 15

A memory control system for a computer comprising: main memory, memory-mapped input/output (I/O) devices, memory control software for causing commands to affect operations at particular addresses, a translation lookaside buffer including memory locations for storing virtual addresses which have been recently accessed and translations of those virtual addresses to physical addresses within the computer, at least one memory position for each memory location recording an indication whether the address is assumed to be memory or memory-mapped I/O, a comparator for detecting whether an instruction accessing a virtual address stored in the translation lookaside buffer presumes that the physical address is the same as the indication recorded for the physical address.

Claim 18

A method of recovering from a failed speculation as claimed in claim 13 in which the step of detecting failure of the speculation includes generating an exception in response to the failure of the speculation.

Claim 19

A method of recovering from a failed speculation as claimed in claim 13 in which the step of providing a process for recovering from an exception related to a failure of the existence of a property of components accessed as memory comprises: storing an exception handler for recovering state of the computer system existing prior to the speculation, and storing an indication of state of the computer system existing prior to the speculation; and in which the step of responding to detection of a failure of the speculation by running the process comprises: recovering the stored indication of state, and continuing with the operation of the computer utilizing the recovered state from the point at which the failed speculation was taken.

Claim 20

A microprocessor comprising: a host processor capable of executing a first instruction set, code morphing software for translating programs written for a target processor having a second different instruction set into instructions of the first instruction set, and a memory controller comprising an address translation buffer including a plurality of storage locations in which recently accessed virtual target addresses and physical addresses represented by the virtual target addresses are to be recorded, each of the storage locations including means for indicating whether a physical address is a memory address or a memory-mapped input/output (I/O) address; and means for comparing an indication in a storage location with a speculation made that an access to a virtual target address in a storage location is to memory or memory-mapped I/O to indicate a subsequent operation to be taken in accessing the address.

Claim 21

A microprocessor comprising: a host processor capable of executing a first instruction set, code morphing software for translating programs written for a target processor having a second different instruction set into instructions of the first instruction set, and a memory controller comprising an address translation buffer including a plurality of storage locations in which recently accessed virtual target addresses and physical addresses represented by the virtual target addresses are to be recorded, each of the storage locations including means for indicating whether a physical address is a memory address or a memory-mapped input/output (I/O) address; and means for comparing an indication in a storage location with a speculation made that an access to a virtual target address in a storage location is to memory or memory-mapped I/O to indicate a subsequent operation to be taken in accessing the address.

Claim 22

A microprocessor as claimed in claim 16 in which the means for comparing an indication in a storage location with a speculation made that an access to a virtual target address in a storage location is to memory or memory-mapped I/O to indicate a subsequent operation taken in accessing the address comprises means for generating an exception in response to a failure of a comparison, and means for responding to the exception to indicate a subsequent operation to be taken in accessing the address.

Claim 23

A microprocessor as claimed in claim 17 in which the means for indicating whether a physical address is a memory address or a memory-mapped input/output (I/O) address comprises a storage position in a storage location.

Claim 24

A memory controller comprising an address translation buffer including a plurality of storage locations in which recently accessed virtual addresses and physical addresses represented by the virtual addresses are to be recorded, each of the storage locations including means for indicating whether a physical address is a memory address or a memory-mapped input/output (I/O) address; and means for comparing an indication in a storage location with a speculation made that an access to an address in a storage location is to memory or memory-mapped I/O to indicate a subsequent operation taken in accessing the address.

Claim 25

A memory controller comprising an address translation buffer including a plurality of storage locations in which recently accessed virtual addresses and physical addresses represented by the virtual addresses are to be recorded, each of the storage locations including means for indicating whether a physical address is a memory address or a memory-mapped input/output (I/O) address; and means for comparing an indication in a storage location with a speculation made that an access to an address in a storage location is to memory or memory-mapped I/O to indicate a subsequent operation taken in accessing the address.

Claim 26

A memory controller as claimed in claim 19 in which the means for comparing an indication in a storage location with a speculation made that an access to an address in a storage location is to memory or memory-mapped I/O to indicate a subsequent operation taken in accessing the address comprises means for generating an exception in response to a failure of a comparison, and means for responding to the exception to indicate a subsequent operation to be taken in accessing the address.

Claim 27

A memory controller as claimed in claim 19 in which the means for indicating whether a physical address is a memory address or a memory-mapped input/output (I/O) address comprises a storage position in a storage location.