US5831323A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having an element isolating oxide film and method of manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1996-02-14
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Granted: 1998-11-03
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Expires: 2016-02-14
Abstract
Abstract There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that tG represents a thickness of a gate electrode layer 6, a height tU to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle theta i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of { theta i, tU +543 0</= theta i</=56.6 DEG , 0</=tU</=0.82tG}. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.
Inventors
- 👤 Kaoru Motonami
- 👤 Shigeru Shiratake
- 👤 Hiroshi Matsuo
- 👤 Yuichi Yokoyama
- 👤 Kenji Morisawa
- 👤 Ritsuko Gotoda
- 👤 Takaaki Murakami
- 👤 Satoshi Hamamoto
- 👤 Kenji Yasumura
- 👤 Yasuyoshi Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:00
CPC Classifications
H; H10; H10W; H10W10/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0149; H10D84/02; H10D84/03; H10D84/038; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0124; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
245 words
A semiconductor device comprising: an element isolating oxide film formed at a predetermined region on a main surface of a semiconductor substrate, said element isolating oxide film including a substantially constant thickness portion and a thickness changing portion, the thickness changing portion including a first portion near the gate insulating film with a relatively small acute angle, not greater than 45°, between the lower surface of the first portion and the lower surface of the gate insulating film, and a second portion near the substantially constant thickness portion with a relatively large acute angle, greater than the relatively small acute angle, between the lower surface of the second portion and the lower surface of the gate insulating film; a gate insulating film formed at a predetermined region in a region on the main surface of said semiconductor substrate not covered with said element isolating oxide film; and a gate electrode layer extending over said element isolating oxide film and said gate insulating film, wherein assuming that t G is a thickness of said gate electrode layer, t U is a height from an upper surface of said gate insulating film to an upper surface of a thickest portion of said element isolating oxide film, and θi is an acute angle between the upper surface of said thickness changing portion and the upper surface of said gate insulating film, said θi and said t U are within the following ranges; 0≦θi≦56.6° 0≦t U ≦0.82t G .
Claim 2
Dependent Claim
245 words
A semiconductor device comprising: an element isolating oxide film formed at a predetermined region on a main surface of a semiconductor substrate, said element isolating oxide film including a substantially constant thickness portion and a thickness changing portion, the thickness changing portion including a first portion near the gate insulating film with a relatively small acute angle, not greater than 45°, between the lower surface of the first portion and the lower surface of the gate insulating film, and a second portion near the substantially constant thickness portion with a relatively large acute angle, greater than the relatively small acute angle, between the lower surface of the second portion and the lower surface of the gate insulating film; a gate insulating film formed at a predetermined region in a region on the main surface of said semiconductor substrate not covered with said element isolating oxide film; and a gate electrode layer extending over said element isolating oxide film and said gate insulating film, wherein assuming that t G is a thickness of said gate electrode layer, t U is a height from an upper surface of said gate insulating film to an upper surface of a thickest portion of said element isolating oxide film, and θi is an acute angle between the upper surface of said thickness changing portion and the upper surface of said gate insulating film, said θi and said t U are within the following ranges; 0≦θi≦56.6° 0≦t U ≦0.82t G .
Claim 3
Dependent Claim
24 words
The semiconductor device according to claim 1, wherein said gate electrode layer has a thickness within a range from 200 Å to 5000 Å.
Claim 4
Dependent Claim
93 words
The semiconductor device according to claim 1, wherein an acute angle defined between a lower surface of a bird's beak of said element isolating oxide film and a lower surface of said gate insulating film at a connection between said bird's beak and a portion other than said bird's beak is smaller than an acute angle defined between a lower surface of the portion other than said bird's beak and the lower surface of said gate insulating film at the connection between said bird's beak and the portion other than said bird's beak.
Claim 5
Dependent Claim
61 words
The semiconductor device according to claim 1, wherein a thickness from the upper surface of said gate insulating film to the upper surface of the thickest portion of said element isolating oxide film is smaller than a thickness from a lower surface of said gate insulating film to a lower surface of the thickest portion of said element isolating oxide film.
Claim 6
Dependent Claim
24 words
The semiconductor device according to claim 1, wherein a channel stopper layer is formed under a lower surface of said element isolating oxide film.
References Cited (Backward Citations)
US4271423A
Cited
JPS6098640A
Cited
US4539744A
Cited
US4622096A
Cited
JPS61189653A
Cited
WO1987001238A1
Cited
JPS6272145A
Cited
JPS62263658A
Cited
JPS6321848A
Cited
US4952525A
Cited
JPH01243447A
Cited
JPH02312234A
Cited
US5554879A
Cited
US5455438A
Cited
JPH05267619A
Cited
JPH05218192A
Cited
JPH0628282A
Cited
US5548147A
Cited
US5686346A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-02 | 2010-05-04 | 2010-11-03 | $7700.00 | Window Closed / Lapsed |