US5826068A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with a serial port having only one pin
Assignee: Microsemi Storage Solutions Inc
•
Filing: 1995-06-07
•
Granted: 1998-10-20
•
Expires: 2015-06-07
Abstract
Abstract A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit. The serial port pin in the host adapter integrated circuit is connected to a shifter circuit in the serial port that serially clocks data from the serial port pin and passes the data parallelly to a bus in the host adapter integrated circuit and vice versa.
Inventors
- 👤 Stillman F. Gates
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:04
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F13/42; G06F13/4282; G06F13/4295
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
209 words
An integrated circuit comprising; a clock terminal; a first module coupled to said clock terminal wherein said first module receives a clock signal from said clock terminal and generates a buffered clock signal, said buffered clock signal and said clock signal having a common frequency; a second module having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said second module; and a serial port having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said serial port and further wherein said serial port further comprises: a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and a bidirectional pin coupled to at least one storage element in said plurality of storage elements wherein said bidirectional pin is the only pin in said serial port, and said bidirectional pin is used to transfer information serially from and to said integrated circuit; wherein said serial port waits for a predetermined time period after transmission of a signal on said bidirectional pin to become sensitive to a signal received on said bidirectional pin.
Claim 2
Dependent Claim
209 words
An integrated circuit comprising; a clock terminal; a first module coupled to said clock terminal wherein said first module receives a clock signal from said clock terminal and generates a buffered clock signal, said buffered clock signal and said clock signal having a common frequency; a second module having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said second module; and a serial port having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said serial port and further wherein said serial port further comprises: a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and a bidirectional pin coupled to at least one storage element in said plurality of storage elements wherein said bidirectional pin is the only pin in said serial port, and said bidirectional pin is used to transfer information serially from and to said integrated circuit; wherein said serial port waits for a predetermined time period after transmission of a signal on said bidirectional pin to become sensitive to a signal received on said bidirectional pin.
Claim 3
Dependent Claim
51 words
An integrated circuit as in claim 1, wherein said plurality of storage elements comprise a plurality of flip-flops, and further wherein said serial port alternately stores in said plurality of storage elements an input signal received from said bidirectional pin and an output signal to be transmitted on said bidirectional pin.
Claim 4
Dependent Claim
54 words
An integrated circuit, as in claim 2, further comprising a plurality of multiplexers, wherein at least one of said multiplexers couples an output terminal of a first flip-flop to an input terminal of a second flip-flop, and further wherein said flip-flops are identical to each other and are clocked by said buffered clock signal.
Claim 5
Dependent Claim
61 words
An integrated circuit as in claim 1 further comprising: a processor data bus; and a processor address bus; wherein said plurality of storage elements are coupled to said processor data bus and said processor address bus so that a processor coupled to said processor data bus and to said processor address bus can load data into said plurality of storage elements.
Claim 6
Dependent Claim
24 words
An integrated circuit as in claim 1 further comprising a shifter state machine wherein said bidirectional pin is coupled to said shifter state machine.
Claim 7
Dependent Claim
64 words
The integrated circuit of claim 1 wherein said serial port further comprises: a line controller circuit coupled to said bidirectional pin; wherein said line controller circuit transfers a first packet serially to said bidirectional pin; and further wherein said line controller circuit receives a second packet serially from said bidirectional pin, said second packet being an acknowledge packet for receipt of said first packet.
Claim 8
Dependent Claim
65 words
The integrated circuit of claim 6, wherein said line controller circuit further comprises a drive line, and said line controller circuit transfers said first packet to said bidirectional pin in response to an active signal on said drive line; and further wherein said line controller circuit receives said acknowledgment packet from said bidirectional pin only in response to an inactive signal on said drive line.
Claim 9
Dependent Claim
85 words
The integrated circuit of claim 6 wherein said line controller circuit comprises (i) an input buffer coupled to said bidirectional pin and (ii) an output driver coupled to said bidirectional pin and to said drive line; wherein an active signal on said drive line enables said output driver to pass said command packet to said bidirectional pin; and further wherein an inactive signal on said drive line disables said output driver to allow said input buffer to receive said acknowledgment packet from said bidirectional pin.
Claim 10
Dependent Claim
43 words
The integrated circuit of claim 8 wherein said output driver in said line controller circuit comprises at least one logic element, said logic element allowing passage of said command packet to said bidirectional pin in dependence on said signal on said drive line.
Claim 11
Dependent Claim
67 words
The integrated circuit of claim 6, wherein said serial port further comprises: a state machine coupled to said line controller circuit, wherein: said state machine drives a first signal active to said line controller circuit to indicate a need to transfer said command packet; and said state machine drives a second signal active to said line controller circuit to indicate a need to receive said acknowledge packet.
Claim 12
Dependent Claim
49 words
The integrated circuit of 10, wherein each of said command packet and said acknowledge packet has a start bit at the beginning and a stop bit at the end, said start bit having a first value and said stop bit having a second value different from said first value.
Claim 13
Dependent Claim
49 words
The integrated circuit of 10, wherein each of said command packet and said acknowledge packet has a start bit at the beginning and a stop bit at the end, said start bit having a first value and said stop bit having a second value different from said first value.
Claim 14
Dependent Claim
22 words
The integrated circuit of claim 11 wherein said bidirectional pin is pulled up to a default value equal to said second value.
Claim 15
Dependent Claim
22 words
The integrated circuit of claim 1, wherein said serial port transmits information on said bidirectional pin synchronous with said buffered clock signal.
Claim 16
Dependent Claim
23 words
The integrated circuit of claim 1 wherein the duration of said predetermined time period is at least two cycles in said clock signal.
Claim 17
Dependent Claim
30 words
The integrated circuit of claim 1 wherein said serial port waits for completion of the signal being received on said bidirectional pin before transmitting another signal on said bidirectional pin.
Claim 18
Dependent Claim
207 words
An integrated circuit comprising: a clock terminal; a first module coupled to said clock terminal wherein said first module receives a clock signal from said clock terminal and generates a buffered clock signal, said buffered clock signal and said clock signal having a common frequency; a second module having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said second module; and a serial port having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said serial port and further wherein said serial port further comprises: a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and a bidirectional pin coupled to at least one storage element in said plurality of storage elements wherein said bidirectional pin is the only pin in said serial port, and said bidirectional pin is used to transfer information serially from and to said integrated circuit; wherein said serial port waits for a predetermined time period after receipt of a signal on said bidirectional pin before transmission of a signal on said bidirectional pin.
Claim 19
Dependent Claim
207 words
An integrated circuit comprising: a clock terminal; a first module coupled to said clock terminal wherein said first module receives a clock signal from said clock terminal and generates a buffered clock signal, said buffered clock signal and said clock signal having a common frequency; a second module having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said second module; and a serial port having a clock input line coupled to said first module wherein said buffered clock signal is supplied to said clock input line of said serial port and further wherein said serial port further comprises: a plurality of storage elements wherein each storage element is serially coupled to another storage element in said plurality of storage elements; and a bidirectional pin coupled to at least one storage element in said plurality of storage elements wherein said bidirectional pin is the only pin in said serial port, and said bidirectional pin is used to transfer information serially from and to said integrated circuit; wherein said serial port waits for a predetermined time period after receipt of a signal on said bidirectional pin before transmission of a signal on said bidirectional pin.
Claim 20
Dependent Claim
50 words
The integrated circuit of claim 16, wherein said plurality of storage elements comprise a plurality of flip-flops, and further wherein said serial port alternately stores in said plurality of storage elements an input signal received from said bidirectional pin and an output signal to be transmitted on said bidirectional pin.
Claim 21
Dependent Claim
35 words
The integrated circuit of claim 17, further comprising a plurality of multiplexers, wherein at least one of said multiplexers couples an output terminal of a first flip-flop to an input terminal of a second flip-flop.
Claim 22
Dependent Claim
60 words
The integrated circuit of claim 16 further comprising: a processor data bus; and a processor address bus; wherein said plurality of storage elements are coupled to said processor data bus and said processor address bus so that a processor coupled to said processor data bus and to said processor address bus can load data into said plurality of storage elements.
Claim 23
Dependent Claim
23 words
The integrated circuit of claim 19 further comprising a shifter state machine wherein said bidirectional pin is coupled to said shifter state machine.
Claim 24
Dependent Claim
22 words
The integrated circuit of claim 16, wherein said serial port transmits data on said bidirectional pin synchronous with said buffered clock signal.
Claim 25
Dependent Claim
62 words
The integrated circuit of claim 16 wherein said serial port further comprises: a line controller circuit coupled to said bidirectional pin; wherein said line controller circuit transmits a first packet serially on said bidirectional pin and said line controller circuit receives a second packet serially from said bidirectional pin, said second packet being an acknowledge packet for receipt of said first packet.
Claim 26
Dependent Claim
65 words
The integrated circuit of claim 22, wherein said line controller circuit further comprises a drive line, and said line controller circuit transfers said first packet to said bidirectional pin in response to an active signal on said drive line; and further wherein said line controller circuit receives said acknowledgment packet from said bidirectional pin only in response to an inactive signal on said drive line.
Claim 27
Dependent Claim
85 words
The integrated circuit of claim 22 wherein said line controller circuit comprises (i) an input buffer coupled to said bidirectional pin and (ii) an output driver coupled to said bidirectional pin and to said drive line; wherein an active signal on said drive line enables said output driver to pass said command packet to said bidirectional pin; and further wherein an inactive signal on said drive line disables said output driver to allow said input buffer to receive said acknowledgment packet from said bidirectional pin.
Claim 28
Dependent Claim
43 words
The integrated circuit of claim 24 wherein said output driver in said line controller circuit comprises at least one logic element, said logic element allowing passage of said command packet to said bidirectional pin in dependence on said signal on said drive line.
Claim 29
Dependent Claim
67 words
The integrated circuit of claim 22, wherein said serial port further comprises: a state machine coupled to said line controller circuit, wherein: said state machine drives a first signal active to said line controller circuit to indicate a need to transfer said first packet; and said state machine drives a second signal active to said line controller circuit to indicate a need to receive said second packet.
Claim 30
Dependent Claim
49 words
The integrated circuit of 26, wherein each of said first packet and said second packet has a start bit at the beginning and a stop bit at the end, said start bit having a first value and said stop bit having a second value different from said first value.
Claim 31
Dependent Claim
49 words
The integrated circuit of 26, wherein each of said first packet and said second packet has a start bit at the beginning and a stop bit at the end, said start bit having a first value and said stop bit having a second value different from said first value.
Claim 32
Dependent Claim
21 words
The integrated circuit of claim 27 wherein said bidirectional pin is pulled to a default value equal to said second value.
Claim 33
Dependent Claim
23 words
The integrated circuit of claim 16 wherein the duration of said predetermined time period is at least two cycles in said clock signal.
Claim 34
Dependent Claim
30 words
The integrated circuit of claim 16 wherein said serial port waits for completion of the signal being received on said bidirectional pin before transmitting another signal on said bidirectional pin.
References Cited (Backward Citations)
GB1584159A
Cited
US4438491A
Cited
US4477882A
Cited
US4597077A
Cited
US4811277A
Cited
US4596010A
Cited
US4656620A
Cited
US4984190A
Cited
US4955305A
Cited
US4982400A
Cited
US5260905A
Cited
US5226040A
Cited
US5280586A
Cited
US5301275A
Cited
US5319754A
Cited
US5233350A
Cited
US5412644A
Cited
US5404527A
Cited
EP0619548A1
Cited
US5430393A
Cited
US5402014A
Cited
US5537558A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |