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Transceiver signal processor for digital cordless communication apparatus

Assignee: Samsung Electronics Co Ltd
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Filing: 1995-03-13
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Granted: 1998-10-20
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Expires: 2015-03-13
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Abstract

Abstract A transceiver signal processor for a digital cordless communication apparatus adopts a heterodyning loop in order to improve the transmitting circuit and power efficiency. The transceiver signal processor adopts an orthogonal demodulation method for a first intermediate frequency, thereby allowing a single reference loop. Since the reference loop itself need not be switched, a frequency drift problem is fundamentally removed.

Inventors

  • 👤 Bo-Gyu Na

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 14:33
CPC Classifications
H; H03; H03D; H03D7/00; H03D7/16; H03D7/161; H03D7/163; H04; H04B; H04B1/00; H04B1/38; H04B1/40; H04B1/403; H04B1/44

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 149 words
A transceiver signal processor for a digital cordless communication apparatus having a transmitter for converting an electrical signal into a radio wave and transmitting said radio wave via an antenna, and a receiver for converting a radio wave received from said antenna into a received electrical signal and processing the received signal, in a communication system using a time-division method by which a frequency channel is divided into constant time intervals for alternating transmission and reception modes of operation, said processor comprising: a frequency synthesizer including a first phase-locked loop (PLL) for channel conversion by which the loop frequency of said first PLL is kept constant by setting an offset corresponding to a received second intermediate frequency to 0 Hz, and a second PLL for high-speed switching between transmit and receive frequencies, by setting the output frequency of said first PLL as a reference signal for said second PLL.
Claim 2
Dependent Claim 149 words
A transceiver signal processor for a digital cordless communication apparatus having a transmitter for converting an electrical signal into a radio wave and transmitting said radio wave via an antenna, and a receiver for converting a radio wave received from said antenna into a received electrical signal and processing the received signal, in a communication system using a time-division method by which a frequency channel is divided into constant time intervals for alternating transmission and reception modes of operation, said processor comprising: a frequency synthesizer including a first phase-locked loop (PLL) for channel conversion by which the loop frequency of said first PLL is kept constant by setting an offset corresponding to a received second intermediate frequency to 0 Hz, and a second PLL for high-speed switching between transmit and receive frequencies, by setting the output frequency of said first PLL as a reference signal for said second PLL.
Claim 3
Dependent Claim 40 words
A transceiver signal processor as claimed in claim 1, further comprising an orthogonal demodulator for receiving an intermediate frequency signal and a frequency derived from said first PLL, and demodulating said intermediate frequency signal to provide a demodulated data signal.
Claim 4
Dependent Claim 31 words
A transceiver signal processor as claimed in claim 1, wherein the frequency of a local oscillator within said second PLL is changed without changing the loop frequency of said first PLL.

References Cited (Backward Citations)

US4862107A Cited
US5194828A Cited
US5319680A Cited
US5144254A Cited
US5150078A Cited
US5422604A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-10-19 2002-04-20 2002-10-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-10-19 2006-04-20 2006-10-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-10-19 2010-04-20 2010-10-20 $7700.00 Window Closed / Lapsed

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