Interface for an asymmetric digital subscriber line transceiver

Claim 2

An interface for a transceiver of a communications system, the interface comprising: a plurality of input ports, each of the input ports for receiving a serial data stream, and for providing parallel data corresponding to the serial data stream; a frame memory, organized as a plurality of channels, the frame memory for receiving the parallel data; a control circuit, coupled to the plurality of input ports and to the frame memory, the control circuit for assigning bytes of the parallel data to the plurality of channels; and a routing table, coupled to the control circuit, which contains addresses, the addresses being used by the control circuit to arbitrarily selectively assign the bytes of the parallel data from any one or more of the plurality of input ports to any one or more channels of the plurality of channels.

Claim 3

The interface of claim 1, wherein the routing table includes a start address and a finish address for the bytes of a selected channel and a current address for a current byte being provided to the frame memory.

Claim 4

The interface of claim 2, wherein the routing table includes special addresses for control information and for synchronization of the plurality of channels.

Claim 5

The interface of claim 3, wherein the frame memory includes a fast path portion and an interleave path portion.

Claim 6

The interface of claim 3, wherein the special addresses include a fast path address and an interleave path address, wherein the fast path address and the interleave path address are used for the synchronization of the plurality of channels.

Claim 7

The interface of claim 5, wherein the special addresses further include control information, wherein the control information contained by the special addresses is defined by the fast path address and the interleave path address.

Claim 8

The interface of claim 6, wherein a host processor generates the start, current, and finish addresses, and provides the start, current, and finish addresses to the routing table.

Claim 9

The interface of claim 7, further comprising: a memory for storing the routing table; a register, having an input coupled to the routing table, for receiving the start, current, and finish addresses for the selected channel, and an output; a multiplexer having a first input coupled to the register for receiving the current addresses, a second input coupled to the register for receiving the special addresses, and for providing one of either the current addresses or the special addresses as necessary to assemble a frame of data from the parallel data; an incrementor, coupled to the register, for incrementing a current address to provide an incremented current address; and a comparator, coupled to the register and to the incrementor, for comparing a finish address to the incremented current address, and if the finish address is equal to the incremented current address, providing a start address to the routing table as a next current address, and if the finish address is not equal to the incremented current address, providing the incremented current address as the next current address.

Claim 10

The interface of claim 1, further comprising: a second frame memory organized as a second plurality of channels, for storing output data in the second plurality of channels; at least one output port, coupled to the second frame memory, for receiving the output data of a channel of the second plurality of channels, and for providing a serial data stream corresponding to the output data; a second control circuit, coupled to the at least one output port and to the second frame memory, the second control circuit for assigning bytes of the output data of the channel to the at least one output port; and a second routing table, coupled to the second control circuit, which contains addresses used to assign the bytes of the output data to the at least one output port.

Claim 11

The interface of claim 9, further comprising: a memory for storing the second routing table; a register, having an input coupled to the second routing table, for receiving start, current, and finish addresses for a selected channel of the second plurality of channels, and an output; a multiplexer having a first input coupled to the output of the register for receiving the current addresses, a second input coupled to the output of the register for receiving special addresses, and for providing one of either the current addresses or the special addresses as necessary to address the second frame memory for retrieving the bytes of the output data; an incrementor, coupled to the register, for incrementing a current address to provide an incremented current address; and a comparator, coupled to the register and to the incrementor, for comparing a finish address to the incremented current address, and if the finish address is equal to the incremented current address, providing a start address to the second routing table as a next current address, and if the finish address is not equal to the incremented current address, providing the incremented current address as the next current address.

Claim 12

The interface of claim 1, wherein the communications system is characterized as being an asymmetric digital subscriber line (ADSL) communications system.

Claim 13

An interface for an asymmetric digital subscriber line (ADSL) communications system transceiver, the interface comprising: a frame memory organized as a plurality of channels, for storing output data in the plurality of channels; a plurality of output ports, each of the plurality of output ports coupled to the frame memory, the plurality of output ports for receiving output data from the plurality of channels, and for providing a serial data stream corresponding to the output data from the plurality of channels; a control circuit, coupled to the plurality of output ports and to the frame memory, the control circuit for assigning bytes of the output data from the the plurality of channels to the plurality of output ports; and a routing table, coupled to the control circuit, which contains addresses used to retrieve bytes of the output data from the frame memory, wherein the addresses are arbitrarily selectively assignable for assigning the bytes of the output data from a selected one or more of the plurality of channels to a selected one or more of the plurality of output ports.

Claim 14

An interface for an asymmetric digital subscriber line (ADSL) communications system transceiver, the interface comprising: a frame memory organized as a plurality of channels, for storing output data in the plurality of channels; a plurality of output ports, each of the plurality of output ports coupled to the frame memory, the plurality of output ports for receiving output data from the plurality of channels, and for providing a serial data stream corresponding to the output data from the plurality of channels; a control circuit, coupled to the plurality of output ports and to the frame memory, the control circuit for assigning bytes of the output data from the the plurality of channels to the plurality of output ports; and a routing table, coupled to the control circuit, which contains addresses used to retrieve bytes of the output data from the frame memory, wherein the addresses are arbitrarily selectively assignable for assigning the bytes of the output data from a selected one or more of the plurality of channels to a selected one or more of the plurality of output ports.

Claim 15

The interface of claim 12, wherein the output data from a selected one of the plurality of channels is provided to at least two of the plurality of output ports.

Claim 16

The interface of claim 12, wherein the routing table includes a start address and a finish address for the bytes of the output data and a current address for a current byte being retrieved from the frame memory.

Claim 17

The interfaceof claim 14, wherein the routing table includes a special address for control information and for synchronization of the plurality of channels.

Claim 18

The interface of claim 15, wherein the frame memory includes a fast path portion and an interleave path portion.

Claim 19

The interface of claim 16, wherein the special address includes a fast path address and an interleave path address, wherein the fast path address and the interleave path address are used for the synchronization of the plurality of channels.

Claim 20

The interface of claim 17, wherein the special address further includes a control address, wherein the control information addressed by the control address is defined by the fast path address and the interleave path address.

Claim 21

The interface of claim 18, wherein a host processor generates the start, current, and finish addresses, and provides the start, current, and finish addresses to the routing table.

Claim 22

An interface for an asymmetric digital subscriber line (ADSL) communications system transceiver, the interface comprising: a frame memory having a fast path portion organized as a first plurality of channels and an interleave path portion as a second plurality of channels, for storing output data in the first and second pluralities of channels; a plurality of output ports, each of the plurality of output ports coupled to the frame memory, a selected output port of the plurality of output ports for receiving output data from a selected one of the first and second pluralities of channels, and for providing a serial data stream corresponding to the output data from the selected one of the first and second pluralities of channels; a routing table including start addresses, current addresses, and finish addresses for retrieving the output data of the selected one of the first and second pluralities of channels; and a control circuit, coupled to the plurality of output ports, to the frame memory, and to the routing table, the control circuit for selecting the start and finish addresses for retrieving the output data.

Claim 23

An interface for an asymmetric digital subscriber line (ADSL) communications system transceiver, the interface comprising: a frame memory having a fast path portion organized as a first plurality of channels and an interleave path portion as a second plurality of channels, for storing output data in the first and second pluralities of channels; a plurality of output ports, each of the plurality of output ports coupled to the frame memory, a selected output port of the plurality of output ports for receiving output data from a selected one of the first and second pluralities of channels, and for providing a serial data stream corresponding to the output data from the selected one of the first and second pluralities of channels; a routing table including start addresses, current addresses, and finish addresses for retrieving the output data of the selected one of the first and second pluralities of channels; and a control circuit, coupled to the plurality of output ports, to the frame memory, and to the routing table, the control circuit for selecting the start and finish addresses for retrieving the output data.

Claim 24

The interface of claim 20, wherein the routing table further comprises special addresses for control information and for synchronization of the first and second pluralities of channels.

Claim 25

The interface of claim 21, wherein the special addresses include a fast path address and an interleave path address, wherein the fast path address and the interleave path address are used for synchronization of the first and second pluralities of channels.

Claim 26

The interface of claim 22, wherein the special addresses further includes control information, wherein the control information contained by the special addresses is defined by the fast path address and the interleave path address.

Claim 27

The interface of claim 23, wherein a host processor generates the start addresses, current addresses, and finish addresses, and provides the start, current, and finish addresses to the routing table.

Claim 28

The interface of claim 23, further comprising: a memory for storing the routing table; a register, having an input coupled to the routing table, for receiving the start and finish addresses and the current addresses for a selected channel of the plurality of channels, and an output; a multiplexer having a first input coupled to the output of the register for receiving the current addresses, a second input coupled to the output of the register for receiving the special addresses, and for providing one of either the current addresses or the special addresses as necessary to address the frame memory for retrieving the output data; an incrementor, coupled to the output of the register, for incrementing a current address to provide an incremented current address; and a comparator, coupled to the output of the register and to the incrementor, for comparing a finish address to the incremented current address, and if the finish address is equal to the incremented current address, providing a start address to the routing table as a next current address, and if the finish address is not equal to the incremented current address, providing the incremented current address as the next current address.