US5825227A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switching circuit at high frequency with low insertion loss
Assignee: Sony Corp
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Filing: 1996-01-18
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Granted: 1998-10-20
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Expires: 2016-01-18
Abstract
Abstract In a switching circuit, low insertion loss and enough isolation can be ensured at a desired frequency at the same time. An inductor is externally connected in parallel with the path between the drain and source of each of field-effect transistors built in a switching integrated circuit, and the inductor and the OFF capacitance of the field-effect transistor are made to generate parallel resonance. At this time, by suitably adjusting the inductance, low insertion loss and enough isolation are ensured at a desired frequency at the same time.
Inventors
- 👤 Kazumasa Kohama
- 👤 Kazuto Kitakubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:38
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H04; H04B; H04B1/00; H04B1/38; H04B1/40; H04B1/44; H04B1/48
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
A switching circuit comprising: first, second and third input/output terminals, a first field-effect transistor having drain and source terminals connected to said first and second input/output terminals respectively, a second field-effect transistor having drain and source terminals connected to said first and third input/output terminals respectively, and first and second impedance elements connected to gate terminals of said first and second field-effect transistors respectively; and first and second inductors connecting said first and second input/output terminals to each other and said first and third input/output terminals to each other respectively; and a third, fourth and fifth impedance elements connected between a bias voltage source and said first, second and third input/output terminals respectively.
Claim 2
Dependent Claim
113 words
A switching circuit comprising: first, second and third input/output terminals, a first field-effect transistor having drain and source terminals connected to said first and second input/output terminals respectively, a second field-effect transistor having drain and source terminals connected to said first and third input/output terminals respectively, and first and second impedance elements connected to gate terminals of said first and second field-effect transistors respectively; and first and second inductors connecting said first and second input/output terminals to each other and said first and third input/output terminals to each other respectively; and a third, fourth and fifth impedance elements connected between a bias voltage source and said first, second and third input/output terminals respectively.
Claim 3
Dependent Claim
39 words
The switching circuit according to claim 1, wherein said first and second field-effect transistors and said first and second impedance elements are formed as an integrated circuit and said first and second inductors are provided outside said integrated circuit.
Claim 4
Dependent Claim
33 words
The switching circuit according to claim 1, further comprising first and second control signals supplied to said gate terminals of said first and second transistors through said first and second impedance elements respectively.
Claim 5
Dependent Claim
34 words
The switching circuit according to claim 3, wherein said first and second inductors each have an inductance which is selected in response to a frequency of said first or second control voltage signal respectively.
Claim 6
Dependent Claim
32 words
The switching circuit according to claim 1, wherein one or more field-effect transistors are connected in series between one of said first and second field-effect transistors and one of said input/output terminals.
Claim 7
Dependent Claim
18 words
The switching circuit according to claim 1, wherein said first and second field-effect transistors are junction field-effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |