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EP0625831A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Radio receiver-transmitter apparatus

Assignee: Sony Corp
•
Filing: 1994-05-20
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Granted: —
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Expires: 2014-05-20
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Abstract

Abstract A radio receiver-transmitter apparatus equipped with a signal changeover switch which is capable of properly dealing with a high-power radio frequency signal and ensuring a desired insertion loss and superior isolation characteristic. The switch has a signal input terminal (12/22), a signal output terminal (14/24) and a signal input-output terminal (11/21), and comprises a 1st FET unit (15/25) connected to the input terminal (12/22) and the input-output terminal (11/21), a 2nd FET unit (16/26) connected to the input terminal (12/22) and the ground, a 3rd FET unit (18/28) connected to the output terminal (14/24) and the input-output terminal (11/21), and a 4th FET unit (17/27) connected to the output terminal (14/24) and the ground. The gate width of each transistor in the 1st FET unit (15/25) is so determined as to render the source-drain saturation current greater than the maximum current amplitude of the input signal fed from the input terminal, and each of the 2nd and 3rd FET units (16,18/26,28) consists of one or more transistor stages equal in number to the result of rounding up the numerical value which is obtained by dividing the maximum voltage amplitude of the input signal fed from the signal input terminal, by the withstand voltage of the transistors in the 2nd and 3rd FET units.

Inventors

  • 👤 Kazumasa Kohama

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 15:53
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H04; H04B; H04B1/00; H04B1/38; H04B1/40; H04B1/44

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 92 words
A radio receiver-transmitter apparatus comprising: an antenna means for transmitting or receiving a radio frequency signal; a switch means connected to said antenna means and comprising at least one FET unit (15-18/25-28) where a plurality of field-effect transistors are mutually connected in series for selectively switching input and output signals via a control means, and FET units each consisting of one or more field-effect transistors; a receiving amplifier to which the output terminal of said switch means is connected; and a transmitting amplifier connected to the output terminal of said switch means.
Claim 2
Dependent Claim 16 words
The radio receiver-transmitter apparatus according to claim 1, wherein said apparatus is a TDMA communication apparatus.
Claim 3
Dependent Claim 18 words
The radio receiver-transmitter apparatus according to claim 1, wherein each of said field-effect transistors is a GaAs FET.
Claim 4
Dependent Claim 23 words
The radio receiver-transmitter apparatus according to claim 1, wherein the field-effect transistors constituting said switch means are connected in series to each other.
Claim 5
Dependent Claim 291 words
A signal changeover switch having a signal input terminal (12/22), a signal output terminal (14/24) and a signal input-output terminal (11/21), and comprising first, second, third and fourth units of field-effect transistors (15-18/25-28); wherein one end of said first FET unit (15) is connected to the signal input terminal (12/22) while the other end thereof is connected to the signal input-output terminal (11/21); one end of said second FET unit (16/26) is connected to the signal input terminal (12/22) while the other end thereof is grounded; one end of said third FET unit (18/28) is connected to the signal output terminal (14/24) while the other end thereof is connected to the signal input-output terminal (11/21); one end of said fourth FET unit (17/27) is connected to the signal output terminal (14/24) while the other end thereof is grounded; each of the transistors constituting said first FET unit (15/25) has a gate width so determined as to render the source-drain saturation current greater than the maximum current amplitude of the input signal fed from the signal input terminal (12/22); said second FET unit (16/26) consists of one or more transistor stages equal in number to the result of rounding up the numerical value which is obtained by dividing the maximum voltage amplitude of the input signal fed from the signal input terminal (12/22), by the withstand voltage of the transistors in said second FET unit; and said third FET unit (18/28) consists of one or more transistor stages equal in number to the result of rounding up the numerical value which is obtained by dividing the maximum voltage amplitude of the input signal fed from the signal input terminal (12/22), by the withstand voltage of the transistors in said third FET unit.
Claim 6
Dependent Claim 74 words
The switch according to claim 5, wherein the number of transistor stages in said first FET unit (15/25) is so determined as to minimize the insertion loss and the isolation value in said first FET units; and the gate width of each of the transistors constituting said second (16/26) and third (18/28) FET units is so determined as to minimize the insertion loss and the isolation value in said second and third FET units.
Claim 7
Dependent Claim 62 words
The switch according to claim 6, wherein the number of transistor stages in said fourth FET unit (17/27) is determined in dependence on the power of the received signal, and the gate width of each of the transistors constituting said fourth FET unit (17/27) is so determined as to minimize the insertion loss and the isolation value in said fourth FET unit.

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