Patent US5824563A successfully refreshed from Google Patents.
US5824563A
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Method for forming lower electrode of capacitor
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-11-17
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Granted: 1998-10-20
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Expires: 2015-11-17
Abstract
Abstract A method for forming the lower electrode of a capacitor used for fabricating a 1-Gbit or above DRAM, using a material having a high dielectric constant, is used in a method for manufacturing a storage capacitor of a VLSI semiconductor device. The lower electrode, which is to be in contact with a high dielectric film, is formed to have a triple-structured storage node pattern. The lowest layer of the lower electrode is formed with TiN which serves as a barrier against the diffusion of impurities from a lower substrate. The middle layer of the lower electrode is formed with RuO 2 which is easy to pattern. The uppermost layer of the lower electrode is formed with Pt which has excellent leakage current properties.
Inventors
- 👤 Cheol-sung Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:51
CPC Classifications
H; H10; H10B; H10B53/00; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/694; H10D1/01; H10D1/041; H10D1/042; H10D1/711; H10D1/716
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
167 words
A method for manufacturing a capacitor, comprising the steps of: forming a conductive plug in an insulating film formed on a semiconductor substrate, the conductive plug having a top surface, the top surface of the conductive plug being planar to a top surface of the insulating film; forming a first layer over the conductive plug and the insulating film, the first layer serving as a barrier layer to prevent diffusion of impurities from the conductive plug and the semiconductor substrate; forming a second layer over the first layer, the second layer comprising a material easier to pattern than Pt; sequentially patterning the second layer and the first layer; forming a third layer over the semiconductor substrate and the patterned second and first layers, the third layer comprising a material having lower leakage current properties than RuO 2 , and etching back the third layer to form an isolated third layer in a cell unit, the isolated third layer being formed over the patterned first and second layers.
Claim 2
Independent Claim
167 words
A method for manufacturing a capacitor, comprising the steps of: forming a conductive plug in an insulating film formed on a semiconductor substrate, the conductive plug having a top surface, the top surface of the conductive plug being planar to a top surface of the insulating film; forming a first layer over the conductive plug and the insulating film, the first layer serving as a barrier layer to prevent diffusion of impurities from the conductive plug and the semiconductor substrate; forming a second layer over the first layer, the second layer comprising a material easier to pattern than Pt; sequentially patterning the second layer and the first layer; forming a third layer over the semiconductor substrate and the patterned second and first layers, the third layer comprising a material having lower leakage current properties than RuO 2 , and etching back the third layer to form an isolated third layer in a cell unit, the isolated third layer being formed over the patterned first and second layers.
Claim 3
Dependent Claim
13 words
A method as recited in claim 1, wherein the first layer comprises TiN.
Claim 4
Dependent Claim
15 words
A method as recited in claim 1, wherein the second layer comprises RuO 2 .
Claim 5
Dependent Claim
13 words
A method as recited in claim 1, wherein the third layer comprises Pt.
Claim 6
Dependent Claim
33 words
A method as recited in claim 1, wherein the steps of forming the first and second layers are performed by depositing the first and second layers by a reactive direct current sputtering process.
Claim 7
Dependent Claim
33 words
A method as recited in claim 1, wherein the step of sequentially patterning the second layer and the first layer is performed by reactive ion etching the second and first layers in sequence.
Claim 8
Dependent Claim
44 words
A method as recited in claim 1, wherein the step of sequentially patterning the second layer and the first layer is performed by etching the second and first layers using a mask pattern having a low etching selectivity with respect to the second layer.
Claim 9
Dependent Claim
14 words
A method as recited in claim 7, wherein the mask pattern comprises silicon-on-glass (SOG).
Claim 10
Dependent Claim
30 words
A method as recited in claim 1, wherein the step of forming a third layer is performed by sputtering a material having lower leakage current properties than RuO 2 .
Claim 11
Dependent Claim
41 words
A method as recited in claim 1, wherein the step of etching back the third layer is followed by the steps of: forming a high dielectric layer over the isolated third layer; and forming a conductive layer over the dielectric layer.
Claim 12
Dependent Claim
41 words
A method as recited in claim 10, wherein the step of forming a high dielectric layer comprises the step of depositing a high dielectric material selected from the group consisting of SrTiO 3 and (Ba x Sr 1-x )TiO 3 .
Claim 13
Dependent Claim
32 words
A method as recited in claim 10, wherein the step of forming a high dielectric layer comprises the step of chemically depositing a high dielectric material to form the high dielectric layer.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |