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US5821605A
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LOC semiconductor package
Assignee: SK Hynix Inc
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Filing: 1995-08-02
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Granted: 1998-10-13
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Expires: 2015-08-02
Abstract
Abstract A semiconductor package is disclosed including a semiconductor chip having a plurality of bonding pads on its top surface; a plurality of inner leads located above the semiconductor chip and electrically connected to the bonding pads by wire; a plurality of outer leads extending from the respective inner leads; and at least one bus bar for power supply and ground formed to be lower than the inner leads above the semiconductor chip. A method of packaging a semiconductor device is disclosed including the steps of: providing a semiconductor chip having a plurality of bonding pads on its top surface; arranging a plurality of inner leads and a plurality of outer leads extending therefrom above the semiconductor chip; and arranging bus bars for power supply and ground to be lower than the inner leads above the semiconductor chip.
Inventors
- 👤 Joon Ki Hong
- 👤 Dong Seok Chun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:35
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W20/44; H10W20/4403; H10W20/4405; H10W70/01; H10W70/04; H10W90/00; H10W90/811; G; G01; G01N; G01N15/00; G01N15/10; G01N2015/1028; H10W72/00; H10W72/071; H10W72/073; H10W72/07351; H10W72/07352; H10W72/30; H10W72/321; H10W72/50; H10W72/551; H10W72/552; H10W72/581; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W74/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
170 words
A semiconductor package comprising: a semiconductor chip having a plurality of bonding pads on its top surface; a plurality of inner leads located above said semiconductor chip; a plurality of outer leads extending from said respective inner leads; at least one bus bar for power supply and ground and extending continuously from part of said plurality of inner leads to under front ends of the plurality of inner leads of said semiconductor chip; a first insulation adhesive tape having a plurality of open areas attaching a top surface of said bus bar to a plurality of bottom surfaces of said front ends of said inner leads; a second insulation adhesive tape attaching a bottom surface of said bus bar to the top surface of said semiconductor chip; a plurality of wires for electrical connection between said inner leads and said bonding pads and between said bus bar and said bonding pads through said open areas; and a compound body molded with all the other package elements excluding said outer leads.
Claim 2
Dependent Claim
170 words
A semiconductor package comprising: a semiconductor chip having a plurality of bonding pads on its top surface; a plurality of inner leads located above said semiconductor chip; a plurality of outer leads extending from said respective inner leads; at least one bus bar for power supply and ground and extending continuously from part of said plurality of inner leads to under front ends of the plurality of inner leads of said semiconductor chip; a first insulation adhesive tape having a plurality of open areas attaching a top surface of said bus bar to a plurality of bottom surfaces of said front ends of said inner leads; a second insulation adhesive tape attaching a bottom surface of said bus bar to the top surface of said semiconductor chip; a plurality of wires for electrical connection between said inner leads and said bonding pads and between said bus bar and said bonding pads through said open areas; and a compound body molded with all the other package elements excluding said outer leads.
Claim 3
Dependent Claim
40 words
A semiconductor package as claimed in claim 1, further comprising: a plurality of conductors coated on the top surface of the front end of said inner leads so as to facilitate wire bonding between said inner leads and bonding pads.
Claim 4
Dependent Claim
24 words
A semiconductor package as claimed in claim 1, wherein said first insulation adhesive tape, second insulation adhesive tape and bus bar are integrally formed.
Claim 5
Dependent Claim
31 words
A semiconductor package as claimed in claim 1, wherein an electrical connection between said bonding pads, said bus bar, and said inner leads forms a power supply and ground electrical path.
Claim 6
Dependent Claim
23 words
A semiconductor package as claimed in claim 1, wherein said bus bar does not extend beyond said front end of said inner leads.
Claim 7
Dependent Claim
38 words
A semiconductor package as claimed in claim 1, wherein said open areas are located adjacent to a group of inner leads, said group of inner leads comprising of at least two inner leads without an open area therebetween.
Claim 8
Dependent Claim
165 words
A semiconductor package comprising: a semiconductor chip having a plurality of bonding pads on its top surface; a plurality of inner leads located above said semiconductor chip; a plurality of outer leads extending from said respective inner leads; at least one bus bar for power supply and ground and extending continuously from part of said plurality of inner leads to under front ends of the plurality of inner leads of said semiconductor chip; a plurality of insulation adhesive islands formed on a top surface of said bus bar and attaching a plurality of bottom surfaces of said front ends of said inner leads to said bus bar; an insulation adhesive tape attaching a bottom surface of said bus bar to the top surface of said semiconductor chip; a plurality of wires for electrical connection between said inner leads and bonding pads and between said bus bar and said bonding pads; and a compound body molded with all the other package elements excluding said outer leads.
Claim 9
Dependent Claim
165 words
A semiconductor package comprising: a semiconductor chip having a plurality of bonding pads on its top surface; a plurality of inner leads located above said semiconductor chip; a plurality of outer leads extending from said respective inner leads; at least one bus bar for power supply and ground and extending continuously from part of said plurality of inner leads to under front ends of the plurality of inner leads of said semiconductor chip; a plurality of insulation adhesive islands formed on a top surface of said bus bar and attaching a plurality of bottom surfaces of said front ends of said inner leads to said bus bar; an insulation adhesive tape attaching a bottom surface of said bus bar to the top surface of said semiconductor chip; a plurality of wires for electrical connection between said inner leads and bonding pads and between said bus bar and said bonding pads; and a compound body molded with all the other package elements excluding said outer leads.
Claim 10
Dependent Claim
40 words
A semiconductor package as claimed in claim 7, further comprising: a plurality of conductors coated on the top surface of the front end of said inner leads so as to facilitate wire bonding between said inner leads and bonding pads.
Claim 11
Dependent Claim
22 words
A semiconductor package as claimed in claim 7, wherein said insulation adhesive islands, bus bar and insulation adhesive tape are integrally formed.
Claim 12
Dependent Claim
31 words
A semiconductor package as claimed in claim 7, wherein an electrical connection between said bonding pads, said bus bar, and said inner leads forms a power supply and ground electrical path.
Claim 13
Dependent Claim
23 words
A semiconductor package as claimed in claim 7, wherein said bus bar does not extend beyond said front end of said inner leads.
Claim 14
Dependent Claim
46 words
A semiconductor package as claimed in claim 7, wherein said electrical connections between said bus bar and said bonding pads are located adjacent to a group of inner leads, the group of inner leads comprising of at least two inner leads without an electrical connection therebetween.
References Cited (Backward Citations)
US5227232A
Cited
US5286999A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |