Fabrication methods for nonvolatile memory devices including extended sidewall electrode

Claim 1

A method of fabricating a nonvolatile semiconductor memory device comprising the steps of: forming on a face of a semiconductor substrate, an insulated floating gate and an insulated control gate on said insulated floating gate, said insulated floating gate and said insulated control gate each including first and second ends, a first sidewall insulating region extending from said substrate face adjacent said first end of said insulated floating gate, across said first end of said insulated floating gate and onto said first end of said control gate and a second sidewall insulating region extending from said substrate face adjacent said second end of said insulated floating gate, across said second end of said insulated floating gate and onto said second end of said insulated control gate; and forming a first extended sidewall electrode on said first sidewall insulating region opposite said insulated floating gate and said insulated control gate, said first extended sidewall electrode extending from adjacent said first end of said insulated control gate and onto said substrate face, and further extending on said substrate face away from said first sidewall insulating region and forming a second sidewall electrode on said second sidewall insulating region opposite said insulated floating gate and said insulated control gate, said second sidewall electrode extending from adjacent said second end of said insulated control gate and onto said substrate face.

Claim 2

A method of fabricating a nonvolatile semiconductor memory device comprising the steps of: forming on a face of a semiconductor substrate, an insulated floating gate and an insulated control gate on said insulated floating gate, said insulated floating gate and said insulated control gate each including first and second ends, a first sidewall insulating region extending from said substrate face adjacent said first end of said insulated floating gate, across said first end of said insulated floating gate and onto said first end of said control gate and a second sidewall insulating region extending from said substrate face adjacent said second end of said insulated floating gate, across said second end of said insulated floating gate and onto said second end of said insulated control gate; and forming a first extended sidewall electrode on said first sidewall insulating region opposite said insulated floating gate and said insulated control gate, said first extended sidewall electrode extending from adjacent said first end of said insulated control gate and onto said substrate face, and further extending on said substrate face away from said first sidewall insulating region and forming a second sidewall electrode on said second sidewall insulating region opposite said insulated floating gate and said insulated control gate, said second sidewall electrode extending from adjacent said second end of said insulated control gate and onto said substrate face.

Claim 8

A method of fabricating a nonvolatile memory device, comprising the steps of: defining an active region and a field region by forming a field oxide layer for device isolation on a semiconductor substrate of a first conductivity type; sequentially forming a gate insulation film and a first conductive layer on the surface of the semiconductor substrate having said field oxide layer formed thereon; forming a patterned conductive layer by patterning said first conductive layer; sequentially forming a first insulation film, a second conductive layer and a second insulation film on the surface of the semiconductor substrate having said patterned conductive layer thereon; forming a gate pattern comprising a second insulation film pattern, a second conductive layer pattern, a first insulation film pattern and a first conductive layer pattern, by patterning said second insulation film, said second conductive layer, said first insulation film and said patterned conductive layer to form a gate electrode including an insulated floating gate and an insulated control gate; forming a sidewall insulation film pattern on both sidewalls of said gate electrode; forming a drain region of a second conductivity type in the active region adjacent one sidewall of said gate electrode; forming a blanket third conductive layer on the semiconductor substrate; patterning the third conductive layer to thereby form a pad layer which electrically contacts the drain region and forms an extended sidewall electrode on said sidewall insulation film pattern opposite said drain region and which partially covers said gate insulation film pattern; and forming a source region of the second conductivity type on the surface of the semiconductor substrate adjacent said extended sidewall electrode.

Claim 9

A method of fabricating a nonvolatile memory device, comprising the steps of: defining an active region and a field region by forming a field oxide layer for device isolation on a semiconductor substrate of a first conductivity type; sequentially forming a gate insulation film and a first conductive layer on the surface of the semiconductor substrate having said field oxide layer formed thereon; forming a patterned conductive layer by patterning said first conductive layer; sequentially forming a first insulation film, a second conductive layer and a second insulation film on the surface of the semiconductor substrate having said patterned conductive layer thereon; forming a gate pattern comprising a second insulation film pattern, a second conductive layer pattern, a first insulation film pattern and a first conductive layer pattern, by patterning said second insulation film, said second conductive layer, said first insulation film and said patterned conductive layer to form a gate electrode including an insulated floating gate and an insulated control gate; forming a sidewall insulation film pattern on both sidewalls of said gate electrode; forming a drain region of a second conductivity type in the active region adjacent one sidewall of said gate electrode; forming a blanket third conductive layer on the semiconductor substrate; patterning the third conductive layer to thereby form a pad layer which electrically contacts the drain region and forms an extended sidewall electrode on said sidewall insulation film pattern opposite said drain region and which partially covers said gate insulation film pattern; and forming a source region of the second conductivity type on the surface of the semiconductor substrate adjacent said extended sidewall electrode.