Patent US4388185A successfully refreshed from Google Patents.
Patent US5819307A successfully refreshed from Google Patents.
US5819307A
Expired / Lapsed
US
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Control method in which frequency of data erasures is limited
Assignee: Socionext Inc
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Filing: 1995-04-28
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Granted: 1998-10-06
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Expires: 2015-04-28
Abstract
Abstract A memory control method includes a first step of managing control information in each of memory blocks constituting the memory, the control information joining the memory blocks in a chain according to the frequency of data erasures occurring in each of the memory blocks; and a second step of determining, on the basis of the control information, a memory block that should be a transfer destination of write data.
Inventors
- 👤 Norishige Iwamoto
- 👤 Hideomi Watanabe
- 👤 Ken Ryu
- 👤 Yasumori Hibi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:59
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/349; G11C16/3495; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G06F2212/00; G06F2212/72; G06F2212/7211
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
100 words
A memory control method for controlling a memory in which a frequency of data erasures that can occur in the memory is limited, said method comprising the steps of: 1) managing control information in each of memory blocks constituting the memory, said control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures; and 2) determining, on the basis of said control information, a memory block that should be a transfer destination of write data.
Claim 2
Dependent Claim
100 words
A memory control method for controlling a memory in which a frequency of data erasures that can occur in the memory is limited, said method comprising the steps of: 1) managing control information in each of memory blocks constituting the memory, said control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures; and 2) determining, on the basis of said control information, a memory block that should be a transfer destination of write data.
Claim 3
Dependent Claim
115 words
The memory control method as claimed in claim 1, wherein said control information includes a contexture defined for each of the memory blocks constituting the memory, and wherein each contexture includes: first pointer information, as said first information, indicating a contexture associated with a memory block having the frequency of data erasures equal to or one step greater than the frequency data erasures associated with the contexture including said first pointer information; and second pointer information, as said second information, indicating a contexture associated with a memory block having the frequency of data erasures equal to or one step lower than the frequency of data erasures associated with the contexture including said second pointer information.
Claim 4
Dependent Claim
34 words
The memory control method as claimed in claim 2, wherein said first step comprises a step of managing only write-enabled memory blocks by joining the memory blocks in a chain using said control information.
Claim 5
Dependent Claim
40 words
The memory control method as claimed in claim 2, further comprising the step of: 3) joining a memory block that has just been write enabled to the chain of the existing memory blocks according to its frequency of data erasures.
Claim 6
Dependent Claim
90 words
The memory control method as claimed in claim 2, further comprising the step of: 3) setting the first and second pointer information associated with the memory block that has just been write enabled, on the basis of the frequency of data erasures of the memory block that has just been write enabled and on the basis of the frequency of data erasures of the other write-enabled memory blocks, such that the memory block that has just been write enabled is built into the chain of the existing write-enabled memory blocks.
Claim 7
Dependent Claim
34 words
The memory control method as claimed in claim 1, wherein said first step comprises a step of managing only write-enabled memory blocks by joining the memory blocks in a chain using said control information.
Claim 8
Dependent Claim
40 words
The memory control method as claimed in claim 1, further comprising the step of: 3) joining a memory block that has just been write enabled to the chain of the existing memory blocks according to its frequency of data erasures.
Claim 9
Dependent Claim
59 words
The memory control method as claimed in claim 1, wherein said second step comprises the step of: searching the chain of memory blocks according to said control information, starting with the memory blocks initially specified by said write data as the transfer destination, and transferring said write data to the memory block having the lowest frequency of data erasures.
Claim 10
Dependent Claim
120 words
A memory control method for controlling a memory in which a frequency of data erasures that can occur in the memory is limited, said method comprising the steps of: 1) selecting a predetermined number of memory blocks constituting the memory and managing the frequency of data erasures of the selected memory blocks by control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures, and 2) determining a memory block that should be a destination of write data such that all or some of the selected memory blocks have the same frequency of data erasures.
Claim 11
Dependent Claim
120 words
A memory control method for controlling a memory in which a frequency of data erasures that can occur in the memory is limited, said method comprising the steps of: 1) selecting a predetermined number of memory blocks constituting the memory and managing the frequency of data erasures of the selected memory blocks by control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures, and 2) determining a memory block that should be a destination of write data such that all or some of the selected memory blocks have the same frequency of data erasures.
Claim 12
Dependent Claim
64 words
The memory control method as claimed in claim 9, wherein said first step comprises the step of: selecting said predetermined number of different memory blocks when some or all of the selected predetermined number of memory blocks have the same frequency of data erasures through the second step, and managing the frequency of data erasures of said selected predetermined number of different memory blocks.
Claim 13
Dependent Claim
40 words
The memory control method as claimed in claim 10, wherein said first step comprises the step of selecting a predetermined number of memory blocks having a relatively low frequency of data erasures or a relatively great frequency of data erasures.
Claim 14
Independent Claim
89 words
An apparatus comprising: a memory in which a frequency of data erasures is limited; first means for managing control information in each of memory blocks constituting the memory, said control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures; and second means for determining, on the basis of said control information, a memory block that should be a transfer destination of write data.
Claim 15
Independent Claim
89 words
An apparatus comprising: a memory in which a frequency of data erasures is limited; first means for managing control information in each of memory blocks constituting the memory, said control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures; and second means for determining, on the basis of said control information, a memory block that should be a transfer destination of write data.
Claim 16
Dependent Claim
45 words
The apparatus as claimed in claim 12, further comprising: a memory in which a frequency of data erasures is not limited; and data transfer control means for controlling data transfer between said memory and the memory in which the frequency of data erasures is limited.
Claim 17
Dependent Claim
44 words
The apparatus as claimed in claim 12, further comprising data transfer control means for controlling data transfer between an externally connected memory in which the frequency of data erasures is not limited and the memory in which the frequency of data erasures is limited.
Claim 18
Independent Claim
93 words
An apparatus for controlling a memory in which a frequency of data erasures is limited, said apparatus comprising: first means for managing control information in each of memory blocks constituting the memory, said control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures; and second means for determining, on the basis of said control information, a memory block that should be a transfer destination of write data.
Claim 19
Independent Claim
93 words
An apparatus for controlling a memory in which a frequency of data erasures is limited, said apparatus comprising: first means for managing control information in each of memory blocks constituting the memory, said control information including first information which joins the memory blocks in an ascending order of frequency of data erasures, and second information which joins the memory blocks in a descending order of frequency of data erasures; and second means for determining, on the basis of said control information, a memory block that should be a transfer destination of write data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-05 | 2002-04-06 | 2002-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-05 | 2006-04-06 | 2006-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-05 | 2010-04-06 | 2010-10-06 | $7700.00 | Window Closed / Lapsed |