Patent US5818261A successfully refreshed from Google Patents.
US5818261A
Expired / Lapsed
US
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Pseudo differential bus driver/receiver for field programmable devices
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-08-08
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Granted: 1998-10-06
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Expires: 2016-08-08
Abstract
Abstract A bus mechanism mitigates programmable device performance and power consumption issues by utilizing a small swing transmitter at the source end of an interconnect network and a high gain differential amplifier at the receiver end of the interconnect network. The signal is generated as a small swing voltage differential compared to a reference voltage and the reference voltage is set at a magnitude close to the negative power supply signal (near ground or GND). Because the performance of NMOS cross point switches with signals close to GND is very good, virtually no signal swing is lost in these NMOS cross point switches. The small swing signal voltages also significantly reduce the power dissipated when transmitting data. Transmitter pre-charge, differential amplifier equalization and a PMOS differential amplifier further enhance performance and reduce power consumption. The bus mechanism is well suited to the general requirements of field programmable devices of providing flexible fan-in, flexible fan-out, and unrestricted interconnect through NMOS cross point switches and large interconnect load capacitances.
Inventors
- 👤 Frederick A. Perner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018528; H03K19/01855
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
64 words
A bus mechanism for a programmable logic device, comprising: a small swing transmitter; a high gain differential amplifier; and a NMOS cross point switch interconnect network coupling the transmitter and the differential amplifier, wherein a signal is generated by the transmitter as a small swing voltage differential from a reference voltage and the signal is compared to the reference voltage by the differential amplifier.
Claim 2
Dependent Claim
64 words
A bus mechanism for a programmable logic device, comprising: a small swing transmitter; a high gain differential amplifier; and a NMOS cross point switch interconnect network coupling the transmitter and the differential amplifier, wherein a signal is generated by the transmitter as a small swing voltage differential from a reference voltage and the signal is compared to the reference voltage by the differential amplifier.
Claim 3
Dependent Claim
32 words
A mechanism as recited in claim 1, further comprising: a level shifter/buffer driver for transforming a limited voltage swing output voltage signal from the differential amplifier to a full CMOS voltage swing.
Claim 4
Dependent Claim
40 words
A mechanism as recited in claim 1, wherein the small swing transmitter includes a reference voltage source for producing the reference voltage and the reference voltage is routed through the NMOS cross point switch interconnect network to the differential amplifier.
Claim 5
Dependent Claim
38 words
A mechanism as recited in claim 1, further including a clocked logic circuit coupled to the small swing transmitter and to the differential amplifier to synchronize precharge of the small swing transmitter with equalization of the differential amplifier.
Claim 6
Dependent Claim
14 words
A mechanism as recited in claim 1, wherein the differential amplifier employs PMOS circuitry.
Claim 7
Dependent Claim
42 words
A mechanism as recited in claim 1, further including a plurality of said small swing transmitters coupled to the NMOS cross point switch interconnect network, wherein only one of the plurality of transmitters is permitted to be active at a given time.
Claim 8
Dependent Claim
23 words
A mechanism as recited in claim 1, further including a plurality of differential amplifiers coupled to the NMOS cross point switch interconnect network.
Claim 9
Dependent Claim
91 words
A bus mechanism for a programmable logic device, comprising: a transmitter circuit including a signal circuit having a pre-charge device and a pull down device; a reference voltage source associated with the transmitter circuit; a receiver circuit having an equalization circuit and a differential amplifier; and interconnect lines including a reference voltage line and a signal line, each of the interconnect lines having a cross point switch, the signal line coupling the signal circuit to the receiver circuit, the reference voltage line coupling the reference voltage source to the receiver circuit.
Claim 10
Dependent Claim
91 words
A bus mechanism for a programmable logic device, comprising: a transmitter circuit including a signal circuit having a pre-charge device and a pull down device; a reference voltage source associated with the transmitter circuit; a receiver circuit having an equalization circuit and a differential amplifier; and interconnect lines including a reference voltage line and a signal line, each of the interconnect lines having a cross point switch, the signal line coupling the signal circuit to the receiver circuit, the reference voltage line coupling the reference voltage source to the receiver circuit.
Claim 11
Dependent Claim
36 words
A mechanism as recited in claim 8, wherein the receiver circuit further includes a level shifter/buffer driver for transforming a limited voltage swing output voltage signal from the differential amplifier to a full CMOS voltage swing.
Claim 12
Dependent Claim
16 words
A mechanism as recited in claim 8, wherein the cross point switch is a NMOS switch.
Claim 13
Dependent Claim
25 words
A mechanism as recited in claim 8, wherein the reference voltage source produces a voltage significantly closer to ground than to full source supply voltage.
Claim 14
Dependent Claim
36 words
A mechanism as recited in claim 8, further including a clocked logic circuit coupled to the transmitter circuit and to the receiver circuit to synchronize precharge of the transmitter circuit with equalization of the receiver circuit.
Claim 15
Dependent Claim
31 words
A mechanism as recited in claim 12, wherein absence of an active pull down on the signal line will cause the differential amplifier to remain at a pre-charge period defined level.
Claim 16
Dependent Claim
14 words
A mechanism as recited in claim 8, wherein the differential amplifier employs PMOS circuitry.
Claim 17
Dependent Claim
56 words
A mechanism as recited in claim 8, further including a plurality of the receiver circuits, wherein the transmitter circuit includes a plurality of the signal circuits; wherein the interconnection lines include a plurality of the signal lines; and wherein each of the signal lines couples one of the signal circuits to one of the receiver circuits.
Claim 18
Dependent Claim
36 words
A mechanism as recited in claim 15, further including a plurality of the transmitter circuits coupled to the signal lines, wherein only one of the transmitter circuits is permitted to be active at a given time.
Claim 19
Dependent Claim
18 words
A mechanism as recited in claim 8, wherein differential amplifier switching is accomplished by setting a current threshold.
Claim 20
Dependent Claim
64 words
A bus method for a programmable logic device, comprising the steps of: generating a signal as a small swing voltage differential from a reference voltage using a small swing transmitter; routing the signal and the reference voltage through a NMOS cross point switch interconnect network coupling the transmitter and a differential amplifier; and comparing the signal to the reference voltage using the differential amplifier.
Claim 21
Dependent Claim
64 words
A bus method for a programmable logic device, comprising the steps of: generating a signal as a small swing voltage differential from a reference voltage using a small swing transmitter; routing the signal and the reference voltage through a NMOS cross point switch interconnect network coupling the transmitter and a differential amplifier; and comparing the signal to the reference voltage using the differential amplifier.
Claim 22
Dependent Claim
35 words
A method as recited in claim 18, further comprising the step of: transforming a limited voltage swing output voltage signal from the differential amplifier to a full CMOS voltage swing using a level shifter/buffer driver.
Claim 23
Dependent Claim
29 words
A method as recited in claim 18, further including the step of: synchronizing precharge of the transmitter circuit with equalization of the differential amplifier using a clocked logic circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-05 | 2002-04-06 | 2002-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-05 | 2006-04-06 | 2006-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-05 | 2010-04-06 | 2010-10-06 | $7700.00 | Window Closed / Lapsed |