Potential generation circuit

Claim 2

A potential generating circuit comprising: at least a first and a second diode connected MOS transistor in series connected between an output node and a given potential node and disposed in the same forward direction, each having a respective back gate always interconnected to a respective gate thereof; and a capacitor coupled between a connection node of said first and second MOS transistors and an input node to which an alternating signal is to be applied.

Claim 3

The potential generating circuit as set forth in claim 1, wherein said first and second MOS transistors are diode-connected and series connected between the output node and a ground potential node so as to be disposed in a forward direction from the output node to the ground potential node.

Claim 4

The potential generating circuit as set forth in claim 1, wherein said first and second MOS transistors are diode-connected and series connected between the output node and a source potential node so as to be disposed in a forward direction from the source potential node to the output node, aid further comprising a charging MOS transistor which is diode-connected between the source potential node and the output node and disposed in a forward direction from the source potential node to the output node, wherein the charging MOS transistor has its back gate and a gate interconnected.

Claim 5

A DRAM comprising a substrate bearing: (a) a memory cell array for storing charge, (b) row and column drivers for addressing the array to access selected cells of the array; and (c) a substrate potential generation circuit applying a prescribed potential to the substrate, comprising at least a first and a second diode-connected MOS transistor connected in series between an output node and a reference node, disposed in the same forward direction and each having a respective gate and a respective back gate always interconnected, capacitor coupled between a node interconnecting said first and second transistors and an input node.

Claim 6

A DRAM comprising a substrate bearing: (a) a memory cell array for storing charge, (b) row and column drivers for addressing the array to access selected cells of the array; and (c) a substrate potential generation circuit applying a prescribed potential to the substrate, comprising at least a first and a second diode-connected MOS transistor connected in series between an output node and a reference node, disposed in the same forward direction and each having a respective gate and a respective back gate always interconnected, capacitor coupled between a node interconnecting said first and second transistors and an input node.

Claim 7

A semiconductor memory device comprising: (a) a memory array including a plurality of memory cells arranged in rows and columns (b) a plurality of word lines arranged corresponding to said rows and each connecting memory cells on a corresponding row; (c) a drive signal generator for generating a drive signal, comprising at least a pair of insulated gate type field effect transistors connected in series between an output node outputting said drive signal and a reference node receiving a reference voltage, disposed in the same forward direction and each having a respective gate and a respective back gate thereof always interconnected, and a capacitor coupled between a node interconnecting said pair of field effect transistors and an input node receiving an alternating signal; and (d) a word driver for transferring the drive signal received from said drive signal generator onto a word line arranged corresponding to an addressed row among said rows.

Claim 8

A semiconductor memory device comprising: (a) a memory array including a plurality of memory cells arranged in rows and columns (b) a plurality of word lines arranged corresponding to said rows and each connecting memory cells on a corresponding row; (c) a drive signal generator for generating a drive signal, comprising at least a pair of insulated gate type field effect transistors connected in series between an output node outputting said drive signal and a reference node receiving a reference voltage, disposed in the same forward direction and each having a respective gate and a respective back gate thereof always interconnected, and a capacitor coupled between a node interconnecting said pair of field effect transistors and an input node receiving an alternating signal; and (d) a word driver for transferring the drive signal received from said drive signal generator onto a word line arranged corresponding to an addressed row among said rows.

Claim 9

The potential generating circuit as set forth in claim 1, wherein, said first diode connected MOS transistor has its back gate connected to its respective gate independent of a conduction state of the second diode connected MOS transistor connected in series.

Claim 10

The potential generating circuit as set forth in claim 4, wherein, said first diode connected MOS transistor has its back gate interconnected to its respective gate independent of a conduction state of the second diode connected MOS transistor connected in series.

Claim 11

A potential generating circuit comprising: at least first and second diode connected MOS transistors connected in series between an output node and a given potential node and disposed in the same forward direction, each having a respective back gate interconnected to a respective gate thereof; and a capacitor coupled between a connection node of said first and second MOS transistors and an input node to which an alternating signal is to be applied.

Claim 12

A potential generating circuit comprising: at least first and second diode connected MOS transistors connected in series between an output node and a given potential node and disposed in the same forward direction, each having a respective back gate interconnected to a respective gate thereof; and a capacitor coupled between a connection node of said first and second MOS transistors and an input node to which an alternating signal is to be applied.