Semiconductor memory device having hierarchical bit line structure

Claim 2

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of sub bit line pairs formed on said semiconductor substrate; a main bit line pair formed along said plurality of sub bit line pairs in a layer located above said plurality of sub bit line a plurality of switching portions each provided corresponding to one of one and the other sub bit lines of said plurality of sub bit line pairs, connected between the corresponding sub bit line and one of one and the other main bit lines of said main bit line pair; a plurality of word lines formed on said semiconductor substrate to cross said plurality of sub bit line pairs; a plurality of memory cells provided corresponding to intersections of said plurality of sub bit line pairs and said plurality of word lines, each connected to one of one and other sub bit lines of the corresponding sub bit line pair and to corresponding word line, said plurality of switching portions each including a selecting transistor formed on said semiconductor substrate and having one source/drain region connected to corresponding sub bit line; a pad connected to the other source/drain region of said selecting transistor and the corresponding main bit line and formed at an intermediate layer between a layer of said plurality of sub bit line pairs and layer of said main bit line pair.

Claim 3

The semiconductor memory device in accordance with claim 1, wherein said main bit line pair is twisted.

Claim 4

The semiconductor memory device in accordance with claim 1, wherein said plurality of memory cells each includes a stacked capacitor having a storage node electrode formed at the same layer as said intermediate layer.

Claim 5

The semiconductor memory device in accordance with claim 3, wherein said pad has a shape which is substantially the same as that of said storage node electrode.

Claim 6

The semiconductor memory device in accordance with claim 1, wherein said main bit line pair is twisted above one of said plurality of switching portions.

Claim 7

The semiconductor memory device in accordance with claim 5, wherein said main bit line pair has a twisted portion above said one of the plurality of switching portions and parallel portions interconnected at said twisted portion, said twisted portion including an upper interconnect segment and a lower interconnect segment, said lower interconnect segment being formed by a layer between the layer of said main bit line pair and the layer of said plurality of sub bit line pairs.

Claim 8

The semiconductor memory device in accordance with claim 6, wherein said plurality of memory cells each includes a stacked capacitor having a strage node electrode formed by the same layer as said layer of said lower interconnect segment.

Claim 9

The semiconductor memory device in accordance with claim 6, wherein said interconnect segment is used as said pad.

Claim 10

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of sub bit line pairs formed in a straight line on said semiconductor substrate, each including one sub bit line; and the other sub bit line located along the extension of said one sub bit line having one end located away from the opposite one end of said one sub bit line; a main bit line pair formed along said plurality of sub bit line pairs in a layer above the layer of said plurality of sub bit line pairs; a plurality of switching portions each provided corresponding to one of one and the other sub bit lines of said plurality of sub bit line pairs, connected between the corresponding sub bit line and one of one and the other main bit lines of said main bit line pair; a plurality of word lines formed on said semiconductor substrate to cross one and the other sub bit lines of said plurality of sub bit line pairs; and a plurality of memory cells provided corresponding to intersections of one and the other sub bit lines of said plurality of sub bit line pairs and said plurality of word lines, each connected to corresponding sub bit line and corresponding word line, said plurality of switching portions each including a selecting transistor formed on said semiconductor substrate having one source/drain region connected to corresponding sub bit line; and a pad connected to the other source/drain region of said selecting transistor and corresponding main bit line, formed at an intermediate layer between the layer of said plurality of sub bit line pair and the layer of said main bit line pair.

Claim 11

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of sub bit line pairs formed in a straight line on said semiconductor substrate, each including one sub bit line; and the other sub bit line located along the extension of said one sub bit line having one end located away from the opposite one end of said one sub bit line; a main bit line pair formed along said plurality of sub bit line pairs in a layer above the layer of said plurality of sub bit line pairs; a plurality of switching portions each provided corresponding to one of one and the other sub bit lines of said plurality of sub bit line pairs, connected between the corresponding sub bit line and one of one and the other main bit lines of said main bit line pair; a plurality of word lines formed on said semiconductor substrate to cross one and the other sub bit lines of said plurality of sub bit line pairs; and a plurality of memory cells provided corresponding to intersections of one and the other sub bit lines of said plurality of sub bit line pairs and said plurality of word lines, each connected to corresponding sub bit line and corresponding word line, said plurality of switching portions each including a selecting transistor formed on said semiconductor substrate having one source/drain region connected to corresponding sub bit line; and a pad connected to the other source/drain region of said selecting transistor and corresponding main bit line, formed at an intermediate layer between the layer of said plurality of sub bit line pair and the layer of said main bit line pair.

Claim 12

The semiconductor memory device in accordance with claim 9, wherein said plurality of memory cells each includes a stacked capacitor having a storage node electrode formed at the same layer as said intermediate layer.

Claim 13

The semiconductor memory device in accordance with claim 10, wherein said pad has a shape which is substantially the same as that of said storage node electrode.

Claim 14

The semiconductor memory device in accordance with claim 9, wherein said main bit line pair has a twisted portion above said one of the plurality of switching portions and parallel portions interconnected at said twisted portion, said twisted portion including an upper interconnect segment and a lower interconnect segment, said lower interconnect segment being formed by a layer between the layer of said main bit line pair and the layer of said plurality of sub bit line pairs.

Claim 15

The semiconductor memory device in accordance with claim 12, wherein said interconnect segment is used as said pad.

Claim 16

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of sub bit line pairs formed on said semiconductor substrate; a main bit line pair formed along said plurality of sub bit line pairs in a layer above the layer of said plurality of sub bit line pairs; a plurality of selecting transistors each provided corresponding to one of one and the other sub bit lines of said plurality of sub bit line pairs, having one source/drain region formed on said semiconductor substrate and connected to corresponding sub bit line; a plurality of word lines formed on said semiconductor substrate to cross said plurality of sub bit line pairs; and a plurality of memory cells provided corresponding to intersections of said plurality of sub bit line pairs and said plurality of word lines each connected to one of one and the other sub bit lines of the corresponding sub bit line pair and to corresponding word line, said main bit line pair having a twisted portion above one of said plurality of selecting transistors; and one and/or the other main bit line of said main bit line pair has a coupling portion at the twisted portion connected to said portions of said one and/or the other main bit line of said main bit line pair said coupling portion being formed in a layer between the layer of the opposing side portion and said plurality of sub bit line pairs.

Claim 17

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of sub bit line pairs formed on said semiconductor substrate; a main bit line pair formed along said plurality of sub bit line pairs in a layer above the layer of said plurality of sub bit line pairs; a plurality of selecting transistors each provided corresponding to one of one and the other sub bit lines of said plurality of sub bit line pairs, having one source/drain region formed on said semiconductor substrate and connected to corresponding sub bit line; a plurality of word lines formed on said semiconductor substrate to cross said plurality of sub bit line pairs; and a plurality of memory cells provided corresponding to intersections of said plurality of sub bit line pairs and said plurality of word lines each connected to one of one and the other sub bit lines of the corresponding sub bit line pair and to corresponding word line, said main bit line pair having a twisted portion above one of said plurality of selecting transistors; and one and/or the other main bit line of said main bit line pair has a coupling portion at the twisted portion connected to said portions of said one and/or the other main bit line of said main bit line pair said coupling portion being formed in a layer between the layer of the opposing side portion and said plurality of sub bit line pairs.

Claim 18

The semiconductor memory device in accordance with claim 14, wherein each of said plurality of memory cells includes a stacked capacitor having a storage node electrode formed in the same layer as the layer of said coupling portion.

Claim 19

The semiconductor memory device in accordance with claim 15, wherein said coupling portion has a shape which is substantially the same as that of said storage node electrode.

Claim 20

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of sub bit line pairs formed on said semiconductor substrate in a straight line, each including one sub bit line; and the other sub bit line located along the extension of said one sub bit line, having one end located away from the opposite one end of said one sub bit line; a main bit line pair formed on said semiconductor substrate along said plurality of sub bit line pairs and having a twisted portion between ends of one sub bit line and the other sub bit line of said plurality of sub bit line pairs; a plurality of selecting transistors each provided corresponding to one of one and the other sub bit lines of said plurality of sub bit line pairs, connected between the other end of corresponding sub bit line and one of one and the other main bit line of said main bit line pair; a plurality of word lines formed on said semiconductor substrate to cross one and the other sub bit lines of said plurality of sub bit line pairs; and a plurality of memory cells provided corresponding to intersections of one and the other sub bit lines of said plurality of sub bit line pairs and said plurality of word lines, each connected to corresponding sub bit line and corresponding word line.

Claim 21

A semiconductor memory device, comprising: a semiconductor substrate; a plurality of sub bit line pairs formed on said semiconductor substrate in a straight line, each including one sub bit line; and the other sub bit line located along the extension of said one sub bit line, having one end located away from the opposite one end of said one sub bit line; a main bit line pair formed on said semiconductor substrate along said plurality of sub bit line pairs and having a twisted portion between ends of one sub bit line and the other sub bit line of said plurality of sub bit line pairs; a plurality of selecting transistors each provided corresponding to one of one and the other sub bit lines of said plurality of sub bit line pairs, connected between the other end of corresponding sub bit line and one of one and the other main bit line of said main bit line pair; a plurality of word lines formed on said semiconductor substrate to cross one and the other sub bit lines of said plurality of sub bit line pairs; and a plurality of memory cells provided corresponding to intersections of one and the other sub bit lines of said plurality of sub bit line pairs and said plurality of word lines, each connected to corresponding sub bit line and corresponding word line.

Claim 22

The semiconductor memory device in accordance with claim 17, wherein one and/or the other main bit line of said main bit line pair includes a coupling portion at the twisted portion connected respectively to opposing side portions of said one and/or the other main bit line of said main bit line pair, said coupling portion being formed in a layer above the layer of the opposing side portions.

Claim 23

The semiconductor memory device in accordance with claim 17, wherein said main bit line pair is formed in a layer above the layer of said plurality of sub bit line pairs; each of said plurality of memory cells includes a stacked capacitor having a storage node electrode formed at a layer between the layer of said main bit line pair and the layer of said plurality of sub bit line pairs; and one and/or the other main bit line of said main bit line pair includes coupling portions at the twisted portions, connected respectively to both side portions of said one and/or the other main bit line of said main bit line pair, said coupling portions being formed at the same layer as the layer of said storage node electrode.

Claim 24

The semiconductor memory device in accordance with claim 19, wherein said coupling portion has a shape which is substantially the same as the shape of said storage node electrode.

Claim 25

In a dynamic random access memory device having a hierarchical bit line structure including a main bit line, a sub bit line formed in a layer located lower than the layer of said main bit line, a word line located to cross said sub bit line, a memory cell connected to said sub bit line and said word line and having a stacked capacitor, and a selecting transistor connected between said main bit line and said sub bit line, an improvement comprising: a pad formed at the same layer as the layer of a storage node electrode of said stacked capacitor, being in contact with said main bit line and a source/drain region of said selecting transistor.

Claim 26

In a dynamic random access memory device having a hierarchical bit line structure including a main bit line, a sub bit line formed in a layer located lower than the layer of said main bit line, a word line located to cross said sub bit line, a memory cell connected to said sub bit line and said word line and having a stacked capacitor, and a selecting transistor connected between said main bit line and said sub bit line, an improvement comprising: a pad formed at the same layer as the layer of a storage node electrode of said stacked capacitor, being in contact with said main bit line and a source/drain region of said selecting transistor.