Patent US5815166A successfully refreshed from Google Patents.
US5815166A
Expired / Lapsed
US
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Graphics subsystem with slaveable rasterizer
Assignee: ZiiLabs Inc Ltd
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Filing: 1995-03-24
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Granted: 1998-09-29
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Expires: 2015-03-24
Abstract
Abstract A graphics processing system with a message-passing architecture, in which the rasterizer can be bypassed by a particular type of message from the host. This permits rasterization to be slaved to the host downloads and bitmasks, so that images and patterns can be applied to lines and polygons, rather than just rectangles as is the case for prior art.
Inventors
- 👤 David Robert Baldwin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:18
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
107 words
A rasterizer comprising: an input interface, connected to receive commands and data; programmable logic connected to receive commands from a preceding subsystem; and to operate in a first or a second mode in accordance with said commands, and when operation in said first mode has been selected, said logic operates in a free-running asynchronous mode to generate a sequence of pixel location identifiers; and when operation in said second mode has been selected, said logic generates individual pixel location identifiers only, and only when individually commanded by one of said commands; and an output interface connected to provide said sequence of pixel location identifiers as an output.
Claim 2
Dependent Claim
107 words
A rasterizer comprising: an input interface, connected to receive commands and data; programmable logic connected to receive commands from a preceding subsystem; and to operate in a first or a second mode in accordance with said commands, and when operation in said first mode has been selected, said logic operates in a free-running asynchronous mode to generate a sequence of pixel location identifiers; and when operation in said second mode has been selected, said logic generates individual pixel location identifiers only, and only when individually commanded by one of said commands; and an output interface connected to provide said sequence of pixel location identifiers as an output.
Claim 3
Dependent Claim
22 words
The rasterizer of claim 1, wherein said output interface provides said sequence of pixel location identifiers to one or more rendering processors.
Claim 4
Dependent Claim
23 words
The rasterizer of claim 1, wherein said programmable logic is connected to receive commands from an external bus through a FIFO buffering stage.
Claim 5
Dependent Claim
99 words
A rasterizer comprising: an input interface, connected to receive commands and data; programmable logic connected to receive commands from a preceding subsystem, and to selectably operate in a free-running asynchronous mode to generate a sequence of pixel location identifiers and associated operation specifiers; wherein said programmable logic generates a sequence of pixel location identifiers with commands which indicate that no action is to be taken for a subset of pixel locations in accordance with a bit masking pattern, if masking has been selected; and an output interface connected to provide said sequence of pixel location identifiers as an output.
Claim 6
Dependent Claim
99 words
A rasterizer comprising: an input interface, connected to receive commands and data; programmable logic connected to receive commands from a preceding subsystem, and to selectably operate in a free-running asynchronous mode to generate a sequence of pixel location identifiers and associated operation specifiers; wherein said programmable logic generates a sequence of pixel location identifiers with commands which indicate that no action is to be taken for a subset of pixel locations in accordance with a bit masking pattern, if masking has been selected; and an output interface connected to provide said sequence of pixel location identifiers as an output.
Claim 7
Dependent Claim
22 words
The rasterizer of claim 4, wherein said output interface provides said sequence of pixel location identifiers to one or more rendering processors.
Claim 8
Dependent Claim
23 words
The rasterizer of claim 4, wherein said programmable logic is connected to receive commands from an external bus through a FIFO buffering stage.
Claim 9
Dependent Claim
85 words
A rasterizer comprising: an input interface, connected to receive commands and data; programmable logic connected to receive commands from a preceding subsystem; and in dependence on said commands, to generate a sequence of pixel location identifiers; wherein said commands include one or more slave-mode commands, and upon receipt of one of said slave-mode commands said rasterizer will simply pass through at least some data received at said input interface; and an output interface connected to provide said sequence of pixel location identifiers as an output.
Claim 10
Dependent Claim
85 words
A rasterizer comprising: an input interface, connected to receive commands and data; programmable logic connected to receive commands from a preceding subsystem; and in dependence on said commands, to generate a sequence of pixel location identifiers; wherein said commands include one or more slave-mode commands, and upon receipt of one of said slave-mode commands said rasterizer will simply pass through at least some data received at said input interface; and an output interface connected to provide said sequence of pixel location identifiers as an output.
Claim 11
Dependent Claim
22 words
The rasterizer of claim 7, wherein said output interface provides said sequence of pixel location identifiers to one or more rendering processors.
Claim 12
Dependent Claim
23 words
The rasterizer of claim 7, wherein said programmable logic is connected to receive commands from an external bus through a FIFO buffering stage.
Claim 13
Independent Claim
111 words
A method for rendering, comprising the steps of: selectably operating programmable rasterizer logic, in a first or a second mode in accordance with commands received from a preceding subsystem, such that when operation in said first mode has been selected, said logic operates in a free-running asynchronous mode to generate a sequence of pixel location identifiers; and when operation in said second mode has been selected, said logic generates individual pixel location identifiers only, and only when individually commanded by one of said commands; and operating one or more rendering processors, which accept the outputs of said rasterizer logic as data and command inputs, to generate and output rendered pixel data.
Claim 14
Independent Claim
111 words
A method for rendering, comprising the steps of: selectably operating programmable rasterizer logic, in a first or a second mode in accordance with commands received from a preceding subsystem, such that when operation in said first mode has been selected, said logic operates in a free-running asynchronous mode to generate a sequence of pixel location identifiers; and when operation in said second mode has been selected, said logic generates individual pixel location identifiers only, and only when individually commanded by one of said commands; and operating one or more rendering processors, which accept the outputs of said rasterizer logic as data and command inputs, to generate and output rendered pixel data.
Claim 15
Dependent Claim
23 words
The method of claim 10, wherein multiple ones of said rendering processors are connected downstream of said rasterizer logic in a pipeline configuration.
Claim 16
Dependent Claim
23 words
The method of claim 10, wherein multiple ones of said rendering processors are connected to operate asynchronously on outputs of said rasterizer logic.
Claim 17
Dependent Claim
42 words
The method of claim 10, wherein multiple ones of said rendering processors are connected to operate on said outputs of said rasterizer logic, and are followed by a frame buffer write stage which writes the rendered pixel data into a frame buffer.
Claim 18
Independent Claim
106 words
A method for rendering, comprising the steps of: selectably operating programmable rasterizer logic, in accordance with commands received from a preceding subsystem, in a free-running asynchronous mode to generate a sequence of pixel location identifiers and associated operation specifiers; wherein said programmable logic generates a sequence of pixel location identifiers with commands which indicate that no action is to be taken for a subset of pixel locations in accordance with a bit masking pattern, if masking has been selected; and operating one or more rendering processors, which accept the outputs of said rasterizer logic as data and command inputs, to generate and output rendered pixel data.
Claim 19
Independent Claim
106 words
A method for rendering, comprising the steps of: selectably operating programmable rasterizer logic, in accordance with commands received from a preceding subsystem, in a free-running asynchronous mode to generate a sequence of pixel location identifiers and associated operation specifiers; wherein said programmable logic generates a sequence of pixel location identifiers with commands which indicate that no action is to be taken for a subset of pixel locations in accordance with a bit masking pattern, if masking has been selected; and operating one or more rendering processors, which accept the outputs of said rasterizer logic as data and command inputs, to generate and output rendered pixel data.
Claim 20
Dependent Claim
23 words
The method of claim 14, wherein multiple ones of said rendering processors are connected downstream of said rasterizer logic in a pipeline configuration.
Claim 21
Dependent Claim
23 words
The method of claim 14, wherein multiple ones of said rendering processors are connected to operate asynchronously on outputs of said rasterizer logic.
Claim 22
Dependent Claim
42 words
The method of claim 14, wherein multiple ones of said rendering processors are connected to operate on said outputs of said rasterizer logic, and are followed by a frame buffer write stage which writes the rendered pixel data into a frame buffer.
Claim 23
Independent Claim
101 words
A method for rasterizing, comprising the steps of: selectably operating programmable rasterizer logic, in accordance with commands received from a preceding subsystem, in a free-running asynchronous mode to generate a sequence of pixel location identifiers and associated operation specifiers; wherein said commands include one or more slave-mode commands, and upon receipt of one of said slave-mode commands said rasterizer will simply pass through at least some data received from the preceding subsystem, without modification; and operating one or more rendering processors, which accept the outputs of said rasterizer logic as data and command inputs, to generate and output rendered pixel data.
Claim 24
Independent Claim
101 words
A method for rasterizing, comprising the steps of: selectably operating programmable rasterizer logic, in accordance with commands received from a preceding subsystem, in a free-running asynchronous mode to generate a sequence of pixel location identifiers and associated operation specifiers; wherein said commands include one or more slave-mode commands, and upon receipt of one of said slave-mode commands said rasterizer will simply pass through at least some data received from the preceding subsystem, without modification; and operating one or more rendering processors, which accept the outputs of said rasterizer logic as data and command inputs, to generate and output rendered pixel data.
Claim 25
Dependent Claim
23 words
The method of claim 18, wherein multiple ones of said rendering processors are connected downstream of said rasterizer logic in a pipeline configuration.
Claim 26
Dependent Claim
23 words
The method of claim 18, wherein multiple ones of said rendering processors are connected to operate asynchronously on outputs of said rasterizer logic.
Claim 27
Dependent Claim
42 words
The method of claim 18, wherein multiple ones of said rendering processors are connected to operate on said outputs of said rasterizer logic, and are followed by a frame buffer write stage which writes the rendered pixel data into a frame buffer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |