Duty cycled control implemented within a frequency synthesizer

Claim 2

A programmable frequency synthesizer comprising: (a) a phase locked loop (PLL) including a current controlled oscillator (ICO), (b) a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, (c) a reference source of signals, (d) a phase-frequency detector for receiving signals from said reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and (e) means for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.

Claim 3

A programmable frequency synthesizer as defined in claim 1 wherein the level translator is comprised of a current mirror for receiving the output signals from the ICO and wherein the means for varying the slew rate is comprised of means for selectively varying a reflected amount of output current of the current mirror to an output terminal of the level translator for providing said output signals from the level translator.

Claim 4

A programmable frequency synthesizer as defined in claim 2 wherein the current mirror is comprised of input field effect transistors (FETs), an output FET and a mirroring FET, and in which the means for varying is comprised of a plurality of FETs having their gates and sources connected in parallel with the mirroring FET and their drains respectively connected in series with the corresponding sources of individual programming FETs, the drains of the programming FETs being connected together and to said output terminal of the level translator, and programming logic signal inputs connected to respective gates of the programming FETs, whereby selectable ones of the programming FETs may be caused to become conductive and thus become parallel current paths with the output FET of the current mirror.

Claim 5

A programmable frequency synthesizer as defined in claim 1 wherein the ICO is comprised of a plurality of inverters connected in series, an output of a final inverter being connected to an input of a first inverter in the series, means for applying variable operating current to the series of inverters whereby the frequency of the ICO can be varied, and means for providing said output signals from the ICO as differential signals from the input of one of the inverters and the output of another inverter spaced an odd number of inverters from said one of the inverters.

Claim 6

A programmable frequency synthesizer as defined in claim 4 in which the odd number of inverters is one.

Claim 7

A programmable frequency synthesizer as defined in claim 4 wherein the ICO is comprised of a plurality of inverters connected in series, an output of a final inverter being connected to an input of a first inverter in the series, means for applying variable operating current to the series of inverters whereby the frequency of the ICO can be varied, and means for providing said output signals from the ICO as differential signals from the input and output of one of the inverters.

Claim 8

A programmable frequency synthesizer comprising: (a) a phase locked loop (PLL) including a current controlled oscillator (ICO), (b) a reference source of signals, (c) a phase-frequency detector, (d) a circuit for applying signals from the reference source to an input of the phase frequency detector, (e) a circuit for applying signals derived from an output of the PLL to another input of the phase-frequency detector, (f) a circuit for providing output signals from the phase-frequency detector to the ICO which are directly proportional to a phase difference between the signals from the reference source and the signals derived from an output of the PLL, and (g) means for varying the slew rate of output signals from the ICO wherein the duty cycle of the output signals may be varied.

Claim 9

A programmable frequency synthesizer comprising: (a) a phase locked loop (PLL) including a current controlled oscillator (ICO), (b) a reference source of signals, (c) a phase-frequency detector, (d) a circuit for applying signals from the reference source to an input of the phase frequency detector, (e) a circuit for applying signals derived from an output of the PLL to another input of the phase-frequency detector, (f) a circuit for providing output signals from the phase-frequency detector to the ICO which are directly proportional to a phase difference between the signals from the reference source and the signals derived from an output of the PLL, and (g) means for varying the slew rate of output signals from the ICO wherein the duty cycle of the output signals may be varied.

Claim 10

A programmable frequency synthesizer as defined in claim 7 wherein the means for varying is comprised of providing a selectable amount of current derived from the output signals from the ICO to an output terminal for supplying said feedback signals.

Claim 11

A programmable frequency synthesizer as defined in claim 8 wherein the means for providing a selectable amount of current is comprised of current switches for carrying said selectable amount of current, having inputs for receiving program signal inputs for enabling and inhibiting said switches.

Claim 12

A programmable frequency synthesizer as defined in claim 8 wherein the ICO is comprised of an oscillator, and including means for varying the oscillation rate by varying current derived from an output of the phase-frequency detector, as said signals provided to the ICO.

Claim 13

A programmable frequency synthesizer comprising a phase locked loop (PLL) including a current control oscillator (ICO) which generates a digital clock signal, the frequency of which is controlled by input current to the ICO, a level transistor which has a finite output slew rate for translating reduced swing output signals from the ICO into fully digital signals, an output buffer for buffering the output of the level translator, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the output buffer and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the output of the output buffer, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current applied to the ICO for control thereof, and apparatus for varying the slew rate of the output signals from the level translator wherein the duty cycle of the output signals may be varied.

Claim 14

A programmable frequency synthesizer comprising a phase locked loop (PLL) including a current control oscillator (ICO) which generates a digital clock signal, the frequency of which is controlled by input current to the ICO, a level transistor which has a finite output slew rate for translating reduced swing output signals from the ICO into fully digital signals, an output buffer for buffering the output of the level translator, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the output buffer and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the output of the output buffer, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current applied to the ICO for control thereof, and apparatus for varying the slew rate of the output signals from the level translator wherein the duty cycle of the output signals may be varied.

Claim 15

A programmable frequency synthesizer comprising a phase locked loop (PLL) including a current controlled oscillator (ICO) which has an internal signal with a finite slew rate, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the ICO and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals form the reference source and the output signals from the output from the ICO, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current that controls the ICO, and apparatus for varying the slew rate of a signal within the ICO wherein the duty-cycle of the output signals may be varied.

Claim 16

A programmable frequency synthesizer comprising a phase locked loop (PLL) including a current controlled oscillator (ICO) which has an internal signal with a finite slew rate, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the ICO and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals form the reference source and the output signals from the output from the ICO, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current that controls the ICO, and apparatus for varying the slew rate of a signal within the ICO wherein the duty-cycle of the output signals may be varied.

Claim 17

A programmable frequency synthesizer comprising a phase locked loop (PLL) including a voltage controlled oscillator (VCO) which has an internal signal with a finite output slew rate, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the VCO and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the output from the VCO, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current that controls the ICO, and apparatus for varying the slew rate of a signal within the VCO wherein the duty-cycle of the output signals may be varied.

Claim 18

A programmable frequency synthesizer comprising a phase locked loop (PLL) including a voltage controlled oscillator (VCO) which has an internal signal with a finite output slew rate, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the VCO and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the output from the VCO, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current that controls the ICO, and apparatus for varying the slew rate of a signal within the VCO wherein the duty-cycle of the output signals may be varied.