US5814537A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming transistor electrodes from directionally deposited silicide
Assignee: Sharp Corp
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Filing: 1996-12-18
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Granted: 1998-09-29
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Expires: 2016-12-18
Abstract
Abstract A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed. Conductive lines, connecting to the electrodes across the field oxide, are fabricated from polycide, which includes a level of polysilicon covered with silicide, when the lower resistance surface of a metal-disilicide overlying the conductive line is required. The method of the present invention is applicable to bulk silicon, as well as SIMOX, transistor fabrication processes. An IC structure having different thicknesses of directionally deposited silicide, and a completed MOS transistor having interim thicknesses of directionally deposited silicide, are also provided.
Inventors
- 👤 Jer-shen Maa
- 👤 Sheng Teng Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:41
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/0212; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
192 words
A method of forming a MOS transistor overlying a substrate of insulating material on an IC comprising the steps of: a) forming source and drain electrodes of silicon overlying the substrate, forming a gate electrode with insulating sidewalls between the source and drain electrodes, and forming insulation material underneath the gate electrode, whereby the insulation electrically isolates the gate electrode from the source and drain electrodes; b) depositing metal-silicide in a collimated path, with the path generally extending perpendicular to the source, drain, and gate electrodes, and parallel to the gate sidewalls, the silicide being selectively applied to the transistor to form a layer of silicide having a first thickness overlying the electrodes and a second thickness, less than the first thickness, overlying the gate sidewall insulation material; and c) isotropically etching the silicide layer deposited in step b) a predetermined thickness, greater than the second thickness but less than the first thickness, to remove the layer of silicide overlying the gate sidewall insulation material, and leaving the electrodes covered with a layer of silicide having a third thickness, whereby the selective formation of silicide on the electrode surfaces increases electrode conductivity.
Claim 2
Independent Claim
192 words
A method of forming a MOS transistor overlying a substrate of insulating material on an IC comprising the steps of: a) forming source and drain electrodes of silicon overlying the substrate, forming a gate electrode with insulating sidewalls between the source and drain electrodes, and forming insulation material underneath the gate electrode, whereby the insulation electrically isolates the gate electrode from the source and drain electrodes; b) depositing metal-silicide in a collimated path, with the path generally extending perpendicular to the source, drain, and gate electrodes, and parallel to the gate sidewalls, the silicide being selectively applied to the transistor to form a layer of silicide having a first thickness overlying the electrodes and a second thickness, less than the first thickness, overlying the gate sidewall insulation material; and c) isotropically etching the silicide layer deposited in step b) a predetermined thickness, greater than the second thickness but less than the first thickness, to remove the layer of silicide overlying the gate sidewall insulation material, and leaving the electrodes covered with a layer of silicide having a third thickness, whereby the selective formation of silicide on the electrode surfaces increases electrode conductivity.
Claim 3
Dependent Claim
67 words
A method as in claim 1 in which an overhang structure overlies the gate electrode, the overhang structure extending beyond the gate electrode to shelter the gate sidewalls from the deposition of silicide when silicide is deposited in a collimated path generally perpendicular to the overhang and parallel to the gate sidewalls, whereby the deposition of silicide on the source and drain electrodes is made more selective.
Claim 4
Dependent Claim
43 words
A method as in claim 2 in which the overhang structure extends beyond the gate electrode a distance generally in the range between 200 and 1000 Å, and in which the second thickness is generally in the range between 0 and 50 Å.
Claim 5
Dependent Claim
54 words
The method as in claim 1 including the further step of: d) annealing the silicide layer having a third thickness formed in step c) to create a disilicide layer having approximately a third thickness, whereby the selective formation of silicide on the electrodes increases the conductivity of the source, drain, and gate electrode surfaces.
Claim 6
Dependent Claim
30 words
A method as in claim 4 in which step d) includes forming disilicide with a rapid-thermal-annealing (RTA) process at a temperature generally in the range between 500° and 900° C.
Claim 7
Dependent Claim
33 words
A method as in claim 5 in which the RTA process of forming disilicide in step d) is completed in a period of time generally in the range between 10 and 50 seconds.
Claim 8
Dependent Claim
159 words
A method as in claim 1 wherein the substrate includes a field area of insulating material generally surrounding the transistor, in which step b) includes depositing a first thickness of metal-silicide on the field area in a collimated path, with the path generally extending perpendicular to the field area, in which step c) includes isotropically etching the silicide layer overlying the field area deposited in step b) a predetermined thickness, greater than the second thickness but less than the first thickness, leaving the field area covered with a layer of silicide having a third thickness, in which step d) includes annealing the silicide overlying the field area to form a disilicide layer, and including the further steps of: e) masking the active areas of the transistor including the source, drain, and gate electrodes; and f) etching the silicide layer from the field area, whereby silicide in the field area is removed to prevent unintended conduction paths across the IC.
Claim 9
Dependent Claim
189 words
A method as in claim 7 in which a polycide conductive line overlies the field area to connect an electrode of the transistor to another region of the IC, the conductive line including a layer of polysilicon overlying the field area, and a first layer of silicide overlying the polysilicon layer, in which step b) includes depositing a first thickness of metal-silicide on the conductive line in a collimated path, with the path generally extending perpendicular to the conductive line, in which step c) includes isotropically etching the silicide layer overlying the conductive line deposited in step b) a predetermined thickness, greater than the second thickness but less than the first thickness, leaving the first layer of silicide covered with a layer of silicide having a third thickness, in which step d) includes annealing both layers of silicide overlying the polysilicon layer of the conductive line, and in which step f) includes etching the third thickness of silicide overlying the conductive line to reveal the first silicide layer, whereby the conductive surfaces of the transistor, including the electrodes and the conductive line, remain covered with silicide to increase conductivity.
Claim 10
Dependent Claim
45 words
A method as in claim 1 in which the first thickness is generally in the range between 100 and 500 Å, the second thickness is between 20 and 100 Å, and in which the third thickness is in the range between 80 and 400 Å.
Claim 11
Dependent Claim
52 words
A method as in claim 1 in which the isotropic etch process of step c) is a process selected from the group consisting of a wet solution etching process, and a dry etching process in a chlorine-containing plasma at high pressure, whereby a minimum of polymer is formed on the gate sidewalls.
Claim 12
Dependent Claim
44 words
A method as in claim 1 in which the source and drain electrodes are formed from bulk silicon deposited on a bulk substrate, and in which the source and drain electrodes are wells in the bulk silicon formed through ion implantation, followed by diffusion.
Claim 13
Dependent Claim
56 words
A method as in claim 1 in which the source and drain electrodes are raised structures formed from epitaxial silicon overlying an active area on an oxide substrate, whereby both the salicidation, and the raising of the source and drain electrodes, permit a reduction in the channel length between electrodes, and therefore, a smaller sized transistor.
Claim 14
Dependent Claim
35 words
A method as in claim 1 in which the deposited metal-silicide is selected from the group consisting of Co, Ti, Ni, W, Mo, Ta, combinations of Ti with Co and Ni, and other refractory metals.
Claim 15
Dependent Claim
35 words
A method as in claim 1 in which the gate electrode is a polycide electrode including a layer of polysilicon overlying the gate insulation layer, and a layer of silicide overlying the layer of polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |