US5812812A
Expired / Lapsed
US
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Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue
Assignee: International Business Machines Corp
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Filing: 1996-11-04
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Granted: 1998-09-22
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Expires: 2016-11-04
Abstract
Abstract A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit. Each of the identified register-dependency units is then translated to its respective instruction utilizing a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle.
Inventors
- 👤 Muhammad Nural Afsar
- 👤 Romesh Mangho Jessani
- 👤 Soummya Mallick
- 👤 Robert Greg McDonald
- 👤 Mukesh Sharma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
167 words
A method of implementing an early data dependency resolution mechanism for an out-of-order instruction issue data processing system, said method comprising the steps of: providing a plurality of cache lines within an instruction cache, wherein each of said plurality of cache lines is capable of storing a plurality of instructions; storing a plurality of non-executable register-dependency units in each of a plurality of cache lines within a register-dependency cache, wherein each of said plurality of non-executable register-dependency units corresponds to a respective instruction within said instruction cache; fetching a plurality of non-executable register-dependency units from said register-dependency cache in a single processor cycle; detecting all non-executable register-dependency units in said fetched plurality of non-executable register-dependency units that have no forward data dependency within said fetched plurality of non-executable register-dependency units; identifying each instruction associated with each of said detected non-executable register-dependency units that have no forward data dependency, within said instruction cache; and permitting all of said identified instructions to be issued within a next processor cycle.
Claim 2
Independent Claim
167 words
A method of implementing an early data dependency resolution mechanism for an out-of-order instruction issue data processing system, said method comprising the steps of: providing a plurality of cache lines within an instruction cache, wherein each of said plurality of cache lines is capable of storing a plurality of instructions; storing a plurality of non-executable register-dependency units in each of a plurality of cache lines within a register-dependency cache, wherein each of said plurality of non-executable register-dependency units corresponds to a respective instruction within said instruction cache; fetching a plurality of non-executable register-dependency units from said register-dependency cache in a single processor cycle; detecting all non-executable register-dependency units in said fetched plurality of non-executable register-dependency units that have no forward data dependency within said fetched plurality of non-executable register-dependency units; identifying each instruction associated with each of said detected non-executable register-dependency units that have no forward data dependency, within said instruction cache; and permitting all of said identified instructions to be issued within a next processor cycle.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein said detecting step further comprises a step of detecting all instructions that are forward data independent utilizing a Tomasulo algorithm.
Claim 4
Dependent Claim
36 words
The method of claim 2 wherein said identifying step further includes a step of identifying all non-executable register-dependency units that are forward data independent within said plurality of non-executable register-dependency units utilizing an Instruction Dispatch Unit.
Claim 5
Dependent Claim
39 words
The method of claim 1 wherein said method further includes a step of associating each of said plurality of cache lines within said register-dependency cache with a corresponding cache line within said instruction cache by a Bus Interface Unit.
Claim 6
Dependent Claim
162 words
A data processing system capable of out-of-order instruction issue, comprising: an instruction cache having a plurality of cache lines, wherein each of said plurality of cache lines stores a plurality of instructions; a register-dependency cache having a plurality of cache lines, wherein each of said plurality of cache lines stores a plurality of non-executable register-dependency units, wherein each of said plurality of non-executable register-dependency units corresponds to a respective instruction within said instruction cache; means for fetching a plurality of non-executable register-dependency units from said register-dependency cache in a single processor cycle; means for detecting all non-executable register-dependency units in said fetched plurality of non-executable register-dependency units that have no forward data dependency within said fetched plurality of non-executable register-dependency units; means for identifying each instruction associated with each of said detected non-executable register-dependency units that have no forward data dependency, within said instruction cache; and means for permitting all of said identified instructions to be issued within a next processor cycle.
Claim 7
Dependent Claim
162 words
A data processing system capable of out-of-order instruction issue, comprising: an instruction cache having a plurality of cache lines, wherein each of said plurality of cache lines stores a plurality of instructions; a register-dependency cache having a plurality of cache lines, wherein each of said plurality of cache lines stores a plurality of non-executable register-dependency units, wherein each of said plurality of non-executable register-dependency units corresponds to a respective instruction within said instruction cache; means for fetching a plurality of non-executable register-dependency units from said register-dependency cache in a single processor cycle; means for detecting all non-executable register-dependency units in said fetched plurality of non-executable register-dependency units that have no forward data dependency within said fetched plurality of non-executable register-dependency units; means for identifying each instruction associated with each of said detected non-executable register-dependency units that have no forward data dependency, within said instruction cache; and means for permitting all of said identified instructions to be issued within a next processor cycle.
Claim 8
Dependent Claim
29 words
The data processing system of claim 5 wherein said detecting means further comprises a means for detecting all instructions that are forward data independent by utilizing a Tomasulo algorithm.
Claim 9
Dependent Claim
35 words
The data processing system of claim 6 wherein said identifying means further includes an Instruction Dispatch Unit for identifying all non-executable register-dependency units that are forward data independent within said plurality of non-executable register-dependency units.
Claim 10
Dependent Claim
40 words
The data processing system of claim 5 wherein said data processing system further includes a Bus Interface Unit for associating each of said plurality of cache lines within said register-dependency cache with a corresponding cache line within said instruction cache.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |