Abstract A digital computer system is described capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
In a digital computer system capable of processing two or more instructions in parallel, the combination comprising: a larger-capacity, lower-speed storage mechanism for storing instructions to be processed; a smaller-capacity, higher-speed storage mechanism for storing instructions with associated tag information; and an instruction compounding mechanism coupled between the lower-speed storage mechanism and the higher-speed storage mechanism for receiving instructions from the lower-speed storage mechanism, for analyzing these instructions and producing tag information which indicates which instructions may be processed in parallel with one another and for supplying these instructions and associated tag information to the higher-speed storage mechanism for storage therein.
Claim 2
Dependent Claim
15 words
The combination of claim 1 wherein the higher-speed storage mechanism is a cache storage mechanism.
Claim 3
Dependent Claim
35 words
The combination of claim 1 or 2 wherein the tag information is comprised of a plurality of tag fields, a different one of which is associated with each instruction analyzed by the instruction compounding mechanism.
Claim 4
Dependent Claim
52 words
The combination of one of claims 1 to 3 wherein the computer system includes a plurality of functional instruction processing units which operate in parallel with one another and the tag information is used in issuing two or more instructions from the higher-speed storage mechanism to different ones of the functional units.
Claim 5
Dependent Claim
95 words
The combination of claim 3 or 4 wherein the instruction compounding mechanism includes: a plural-instruction instruction register for receiving a plurality of successive instructions from the lower-speed storage mechanism; a plurality of rule-based instruction analyzer mechanisms, each of which analyzes a different pair of side-by-side instructions in the instruction register and produces a compoundability signal which indicates whether or not the two instructions in its pair may be processed in parallel; and a tag generating mechanism responsive to the compoundability signals for generating the individual tag fields for the different instructions in the instruction register.
Claim 6
Dependent Claim
59 words
The combination of claim 5 wherein: the computer system has a particular instruction processing configuration; and each instruction analyzer mechanism includes logic circuitry for implementing rules which define which types of instructions are compatible for parallel execution in the particular instruction processing configuration used for the computer system, such logic circuitry producing the compoundability signal for that analyzer mechanism.
Claim 7
Dependent Claim
133 words
In a digital computer system capable of processing two or more instructions in parallel, the combination comprising: a first storage mechanism for storing instructions to be processed; an instruction compounding mechanism for receiving instructions from the first storage mechanism and associating with these instructions tag fields which indicate which of these instructions may be processed in parallel with one another; a further storage mechanism coupled to the instruction compounding mechanism for receiving and storing the instructions and their associated tag fields; a plurality of functional instruction processing units which operate in parallel with one another; and an instruction issue mechanism coupled to the further storage mechanism for supplying adjacent instructions stored therein to different ones of the functional instruction processing units when their tag fields indicate that they may be processed in parallel.
Claim 8
Dependent Claim
17 words
The combination of claim 7 wherein the further storage mechanism is a small-capacity, high-speed cache storage mechanism.
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