Soft-switching driver output stage and method

Claim 2

A circuit for driving a power transistor, said circuit comprising: a first switch circuit for supplying a first gate drive voltage to the gate of said power transistor, said first gate drive voltage having a value slightly above the threshold voltage of the power transistor; a second switch circuit for supplying a second gate drive voltage to the gate of said power transistor, said second gate drive voltage being a supply voltage; and a timing circuit for gating on one of said first and second switch circuits and for gating off the other of said first and second switch circuits, such that when there is a change of state in an input voltage, said first switch circuit is initially turned on and said second switch circuit is initially turned off, and after a predetermined interval, said first switch circuit is turned off and said second switch circuit is turned on, thereby providing a soft turn-on of said power transistor and reducing current transients.

Claim 3

The circuit of claim 1 wherein the power transistor is a first one of first and second power transistors arranged in series in a half-bridge configuration, wherein said circuit provides a soft turn-on of said first power transistor and reduces current transisents in said second power transistor.

Claim 4

The circuit of claim 1 further comprising a third switch circuit for pulling down the voltage supplied to said gate of said power transistor to its source potential when there is a further change of state in said input voltage, so that said power transistor is turned off.

Claim 5

The circuit of claim 3, wherein said second switch circuit is gated off when said input voltage further changes state.

Claim 6

The circuit of claim 1 wherein said second switch circuit includes an amplifier circuit and a voltage reference circuit.

Claim 7

The circuit of claim 5 wherein said amplifier includes a transistor in a common drain configuration.

Claim 8

The circuit of claim 6 wherein said voltage reference circuit includes a steady state bias current source, and a control circuit for controlling said common drain configured transistor.

Claim 9

The circuit of claim 1 wherein said timing circuit includes a pulse generator circuit that generates a pulse for the duration of said predetermined interval that initiates the turning on of said first switch circuit.

Claim 10

The circuit of claim 8 wherein when said pulse is terminated by said pulse generator circuit, said first switch is turned off and said second switch is turned on so that said second gate drive voltage is supplied to the gate of said power transistor.

Claim 13

The method of claim 10 wherein the power transistor is a first one of first and second power transistors arranged in series in a half-bridge configuration, wherein said circuit provides a soft turn-on of said first power transistor and reduces current transisents in said second power transistor.

Claim 14

The method of claim 10 further comprising the step of turning off the first power transistor when said input voltage further changes state.

Claim 15

The method of claim 10 wherein a pulse is generated for the duration of said predetermined interval and which initiates supplying said first gate drive voltage to the gate of said power transistor.

Claim 16

The method of claim 13 wherein the termination of said pulse at the end of said predetermined interval initiates supplying the second gate drive voltage to the gate of said power transistor.

Claim 17

A circuit for turning on and off an MOS-gated power transistor, said circuit comprising: a first switch circuit for supplying a first gate drive voltage to said MOS-gated power transistor, said first gate drive voltage having a value slightly above the threshold voltage of said MOS-gated power transistor; a second switch circuit for supplying a second gate drive voltage to said gate of said MOS-gated power transistor, said second gate drive voltage being a supply voltage; and a timing circuit for gating on one of said first and second switch circuits and for gating off the other one of said first and second switch circuits such that when there is a change of state in an input voltage, said first switch circuit is initially turned on and said second switch circuit is initially turned off and, after a predetermined interval, said first switch circuit is turned off and said second switch circuit is turned on, thereby providing a soft turn-on of said MOS-gated power transistor and reducing current transients.

Claim 18

A circuit for turning on and off an MOS-gated power transistor, said circuit comprising: a first switch circuit for supplying a first gate drive voltage to said MOS-gated power transistor, said first gate drive voltage having a value slightly above the threshold voltage of said MOS-gated power transistor; a second switch circuit for supplying a second gate drive voltage to said gate of said MOS-gated power transistor, said second gate drive voltage being a supply voltage; and a timing circuit for gating on one of said first and second switch circuits and for gating off the other one of said first and second switch circuits such that when there is a change of state in an input voltage, said first switch circuit is initially turned on and said second switch circuit is initially turned off and, after a predetermined interval, said first switch circuit is turned off and said second switch circuit is turned on, thereby providing a soft turn-on of said MOS-gated power transistor and reducing current transients.

Claim 19

The circuit of claim 15 further comprising a third switch circuit for pulling down the voltage supplied to said gate of said MOS-gated power transistor to its source potential when there is a further change of state in said input voltage, so that said MOS-gated power transistor is turned off.

Claim 20

The circuit of claim 16, wherein said second switch circuit is gated off when said input voltage further changes state.

Claim 21

The circuit of claim 15 wherein said first switch circuit includes an amplifier circuit and a voltage reference circuit.

Claim 22

The circuit of claim 18 wherein said amplifier includes a transistor in a common drain configuration.

Claim 23

The circuit of claim 19 wherein said voltage reference circuit includes a steady state bias current source, and a transistor switch and a zener diode for controlling said common drain configured transistor.

Claim 24

The circuit of claim 15 wherein said timing circuit includes a pulse generator circuit that generates a pulse for the duration of said predetermined interval that initiates the turning on of said first switch circuit.

Claim 25

The circuit of claim 21 wherein when said pulse is terminated by said pulse generator circuit, said first switch circuit is turned off and said second switch circuit is turned on so that said second gate drive voltage is supplied to the gate of said power transistor.

Claim 28

The method of claim 23 further comprising the step of turning off said MOS-gated power transistor when said input voltage further changes state.

Claim 29

The method of claim 23 wherein a pulse is generated for the duration of said predetermined interval which initiates supplying said first gate drive voltage to said gate of said first MOS-gated power transistor.

Claim 30

The method of claim 25 wherein termination of said pulse at the end of said predetermined interval initiates supplying said second gate voltage to said gate of said MOS-gated power transistor.