Single-side oxide sealed salicide for EPROMS

Claim 1

A semiconductor structure of the type suitable for use in an electrically-erasable read only memory or a Flash memory cell, comprising: a semiconductor substrate of a first conductivity type, a source region having a second conductivity type opposite said first conductivity type in said substrate, at least one drain region having said second conductivity type formed in said substrate adjacent to a surface of said substrate, a layer of a first dielectric material formed over said substrate including a tunned dielectric region, at least one floating gate of a first conductive material disposed on said layer of first dielectric material overlaying substantially said tunnel dielectric region, a layer of a second dielectric material disposed on said at least one floating gate, at least one control gate of a second conductive material formed on said layer of second dielectric material; a layer of a third dielectric material disposed on a portion of said second dielectric material, on a portion of said control gate, on said source region, and on one edge of said at least one control gate as a sidewall spacer, and a metal silicide layer hi substantially the same thickness disposed side-by-side with said layer of the third dielectric material on areas not covered by said layer of the third dielectric material including at least a portion of said at least one control gate and said at least one drain regions, said layer of the third dielectric material having a thickness sufficient to electrically insulate said at least one floating gate and said at least one control gate so as to prevent the occurrence of a silicide bridge between said at least one floating gate and said source region, and between said at least one control gate and said drain region.