Patent US5809340A successfully refreshed from Google Patents.
US5809340A
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Adaptively generating timing signals for access to various memory devices based on stored profiles
Assignee: NEC Corp
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Filing: 1997-08-12
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Granted: 1998-09-15
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Expires: 2017-08-12
Abstract
Abstract Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.
Inventors
- 👤 James F. Bertone
- 👤 Bruno DiPlacido, Jr.
- 👤 Thomas F. Joyce
- 👤 Martin Massucci
- 👤 Lance J. McNally
- 👤 Thomas L. Murray, Jr.
- 👤 Chester M. Nibby, Jr.
- 👤 Michelle A. Pence
- 👤 Marc Sanfacon
- 👤 Jian-Kuo Shen
- 👤 Jeffrey S. Somers
- 👤 G. Lewis Steiner
- 👤 William S. Wu
- 👤 Norman J. Rasmussen
- 👤 Suresh K. Marisetty
- 👤 Puthiya K. Nizar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:15
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1694; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F13/1605; G06F13/1652; G06F13/1657; G06F13/1689; G06F13/36; G06F13/368
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
119 words
A memory controller for adaptively generating timing signals for controlling a plurality of memory elements in a computer system, comprising: a means for providing a plurality of timing characteristics values representing timing characteristics of memory circuits; a timing calculator means responsive to the timing characteristic values for calculating a plurality of timing control values representing time intervals between memory timing events, the timing control values including first timing control values representing timing events relative to the start of a memory operation cycle, and second timing control values representing timing events relative to other timing events; and, a state machine responsive to the first and second timing control values for generating timing signals for controlling operation of the memory elements.
Claim 2
Dependent Claim
119 words
A memory controller for adaptively generating timing signals for controlling a plurality of memory elements in a computer system, comprising: a means for providing a plurality of timing characteristics values representing timing characteristics of memory circuits; a timing calculator means responsive to the timing characteristic values for calculating a plurality of timing control values representing time intervals between memory timing events, the timing control values including first timing control values representing timing events relative to the start of a memory operation cycle, and second timing control values representing timing events relative to other timing events; and, a state machine responsive to the first and second timing control values for generating timing signals for controlling operation of the memory elements.
Claim 3
Dependent Claim
221 words
A memory controller for adaptively generating timing signals for controlling one or more memory elements having coded timing values in a computer system, comprising: means for reading and decoding the coded memory element timing values present in the memory elements; means for storing one or more profiles of said one or more memory elements that may be controlled by said memory controller, said one or more profiles comprising timing characteristics of said one or more memory elements; means for automatically selecting said one or more profiles based on the coded timing values, said one or more profiles corresponding to said one or more memory elements in the computer system for adaptively providing a plurality of predetermined timing characteristics values representing timing characteristics of the memory circuits in the computer system based on said timing characteristics values; means responsive to the timing characteristics values for calculating a plurality of timing control values representing time intervals between memory timing events, the timing control values including first timing control values representing memory timing events relative to the start of a memory operation cycle, and second timing control values representing memory timing events relative to other memory timing events; and a state machine responsive to the first and second timing control values for generating actual timing signals for adaptively controlling operation of the memory elements.
Claim 4
Dependent Claim
221 words
A memory controller for adaptively generating timing signals for controlling one or more memory elements having coded timing values in a computer system, comprising: means for reading and decoding the coded memory element timing values present in the memory elements; means for storing one or more profiles of said one or more memory elements that may be controlled by said memory controller, said one or more profiles comprising timing characteristics of said one or more memory elements; means for automatically selecting said one or more profiles based on the coded timing values, said one or more profiles corresponding to said one or more memory elements in the computer system for adaptively providing a plurality of predetermined timing characteristics values representing timing characteristics of the memory circuits in the computer system based on said timing characteristics values; means responsive to the timing characteristics values for calculating a plurality of timing control values representing time intervals between memory timing events, the timing control values including first timing control values representing memory timing events relative to the start of a memory operation cycle, and second timing control values representing memory timing events relative to other memory timing events; and a state machine responsive to the first and second timing control values for generating actual timing signals for adaptively controlling operation of the memory elements.
Claim 5
Dependent Claim
20 words
The memory controller of claim 2 wherein the timing characteristics values further represent timing characteristics of memory data transfer buses.
Claim 6
Dependent Claim
30 words
The memory control of claim 2 wherein the memory elements operate in interleaved memory cycles and the timing control values further represent memory timing events for interleaving of memory cycles.
Claim 7
Dependent Claim
152 words
A memory controller for adaptively generating timing signals for controlling one or more memory elements having various timing characteristics in a computer system, comprising: means for providing a plurality of timing control values representing said various timing characteristics, the timing control values including first timing control values representing memory timing events relative to the start of a memory operation cycle, and second timing control values representing memory timing events relative to other memory timing events; means for storing said first and said second control values for use by the memory controller, said storing means further storing a plurality of said first and said second control values wherein said plurality of said first and said second control values correspond to said one or more memory elements; and a state machine responsive to the first and second timing control values for automatically generating actual timing signals for adaptively controlling operation of the memory elements.
Claim 8
Dependent Claim
152 words
A memory controller for adaptively generating timing signals for controlling one or more memory elements having various timing characteristics in a computer system, comprising: means for providing a plurality of timing control values representing said various timing characteristics, the timing control values including first timing control values representing memory timing events relative to the start of a memory operation cycle, and second timing control values representing memory timing events relative to other memory timing events; means for storing said first and said second control values for use by the memory controller, said storing means further storing a plurality of said first and said second control values wherein said plurality of said first and said second control values correspond to said one or more memory elements; and a state machine responsive to the first and second timing control values for automatically generating actual timing signals for adaptively controlling operation of the memory elements.
References Cited (Backward Citations)
US4785416A
Cited
US4755964A
Cited
JPS6278640A
Cited
US4860291A
Cited
JPH01235409A
Cited
US5522064A
Cited
DE4204730A1
Cited
US5428746A
Cited
US5418924A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |