Patent US5809334A successfully refreshed from Google Patents.
US5809334A
Expired / Lapsed
US
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Receive packet pre-parsing by a DMA controller
Assignee: Allen Bradley Co LLC
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Filing: 1996-09-24
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Granted: 1998-09-15
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Expires: 2016-09-24
Abstract
Abstract A processor-based control system including a host processor, a data receiver device, a system memory, and an intelligent DMA controller. The DMA controller includes a pre-parsing section. The pre-parsing section interrogating a received data packet to determine whether the received data packet contains an error, is valid, is a null packet or whether the host processor must be contacted.
Inventors
- 👤 Daniel J. Galdun
- 👤 Peter J. Boldt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
199 words
A method of transmitting data packets in a processor based control system wherein a host processor processes the data packets, the method comprising the steps of: receiving and storing data from an external source in an external data receiving device; issuing an interrupt signal from the external data receiving device to a DMA controller requesting movement of the data, formed as a data packet, from the external data receiving device to a system memory; issuing a data transfer complete interrupt signal from the external data receiving device to the DMA controller indicating the data packet has been transferred; pre-parsing, by the DMA controller, the received data packet prior to the data packet being processed by the host processor, the pre-processing including interrogating the external data receiving device, by the DMA controller, as to whether a received data packet contains an error, is valid, is a null packet or whether the external data receiving device requires attention from the host processor; and marking the moved data packet by the DMA controller dependent upon results of the interrogation of the data packet by the DMA controller, the marked data packet being provided at a location for processing by a host processor.
Claim 2
Independent Claim
199 words
A method of transmitting data packets in a processor based control system wherein a host processor processes the data packets, the method comprising the steps of: receiving and storing data from an external source in an external data receiving device; issuing an interrupt signal from the external data receiving device to a DMA controller requesting movement of the data, formed as a data packet, from the external data receiving device to a system memory; issuing a data transfer complete interrupt signal from the external data receiving device to the DMA controller indicating the data packet has been transferred; pre-parsing, by the DMA controller, the received data packet prior to the data packet being processed by the host processor, the pre-processing including interrogating the external data receiving device, by the DMA controller, as to whether a received data packet contains an error, is valid, is a null packet or whether the external data receiving device requires attention from the host processor; and marking the moved data packet by the DMA controller dependent upon results of the interrogation of the data packet by the DMA controller, the marked data packet being provided at a location for processing by a host processor.
Claim 3
Dependent Claim
77 words
The method according to claim 1 wherein when the interrogation determines the data packet is valid, the method further comprises the steps of: completing interrupt handshaking between the DMA controller and the external data receiving device; marking the data packet as valid by the DMA controller; updating a buffer descriptor which is in place between the DMA controller and the host processor; and passing information regarding the data packet from the DMA controller to the host processor.
Claim 4
Dependent Claim
79 words
The method according to claim 1 wherein when the interrogation determines the data packet contains an error, the method further comprises the steps of: completing interrupt handshaking between the DMA controller and the external data receiving device; marking the data packet as having an error by the DMA controller; updating a buffer descriptor which is in place between DMA controller and the host processor; and passing information regarding the data packet from the DMA controller to the host processor.
Claim 5
Dependent Claim
47 words
The method according to claim 1 wherein when the interrogation determines the data packet is a null packet, the method further comprising the steps of: completing interrupt handshaking between the DMA controller and the external receiving device; and entering a wait state for a next data packet.
Claim 6
Dependent Claim
88 words
The method according to claim 1 wherein when the signal issued from the external data receiving device to the DMA controller is not supported by the DMA controller, the method further comprising the steps of: issuing a signal from the DMA controller to the host processor informing the host processor that the DMA controller does not support the interrupt from the external data receiving device; causing the host processor to complete interrupt processing with the external data receiving device; and processing the data packet by the host processor.
Claim 7
Dependent Claim
152 words
A control system comprising: an external data receiver device configured to receive and store, as a data packet, externally generated data and further configured to issue an interput signal; a DMA controller configured to access the stored data from the external data receiver device based on the interrupt signal from the external data receiving device, the DMA controller further configured with a pre-parsing section used to act on a received data packet, prior to the data packet being processed by a host processor, the pre-parsing section including a means for interrogating the external data receiving device to determine if the data packet is a valid data packet, a data packet with an error, or a null packet the DMA controller further configured with a means for marking the received data packet in accordance with the interrogation; and a system memory configured to store the data packet from the external data receiver device.
Claim 8
Dependent Claim
152 words
A control system comprising: an external data receiver device configured to receive and store, as a data packet, externally generated data and further configured to issue an interput signal; a DMA controller configured to access the stored data from the external data receiver device based on the interrupt signal from the external data receiving device, the DMA controller further configured with a pre-parsing section used to act on a received data packet, prior to the data packet being processed by a host processor, the pre-parsing section including a means for interrogating the external data receiving device to determine if the data packet is a valid data packet, a data packet with an error, or a null packet the DMA controller further configured with a means for marking the received data packet in accordance with the interrogation; and a system memory configured to store the data packet from the external data receiver device.
Claim 9
Dependent Claim
26 words
The control system according to claim 6 wherein the system memory is further configured to provide access to the stored data packet by the host processor.
Claim 10
Dependent Claim
29 words
The control system according to claim 7 wherein the DMA controller is further configured to inform the host processor of interrupts the DMA controller is not capable of supporting.
Claim 11
Dependent Claim
71 words
The control system according to claim 6 further comprising: a data request line configured to carry a DMA interrupt request from the external data receiving device, when the external data receiving device contains data on its internal buffer; and a frame complete interrupt line configured to carry a frame complete interrupt signal from the external data receiving device to indicate all data in the external data receiving device has been sent.
Claim 12
Dependent Claim
19 words
The control system according to claim 6 wherein the external data receiving device is a media access interface chip.
Claim 13
Dependent Claim
114 words
The control system according to claim 6 further including: an interrupt signal issuing means of the external data receiving device for issuing an interrupt signal to a DMA controller requesting movement of the data, formed as the data packet, from the external data receiving device to the system memory; a data transfer complete interrupt signal issuing means of the external data receiving device for issuing a data transfer complete interrupt signal to the DMA controller indicating the data packet has been transferred; an interrogation means of the DMA controller for interrogating the data packets; and a means for marking the received data packet by the DMA controller dependent upon the results of the interrogation.
Claim 14
Dependent Claim
34 words
The method according to claim 11 wherein the interrogation means includes means to determine whether the data packet is a valid data packet, a data packet with an error, or a null data packet.
Claim 15
Dependent Claim
115 words
An intelligent DMA controller comprising: a channel for receiving and transmitting data, in the form of a data packet, to and from the DMA controller; a plurality of internal control registers used to control the transmitting of the data packet through the data channel; and a pre-parsing section configured to determine the status of a received data packet prior to the data packet being processed by a host processor, the pre-parsing section including a means for interrogating an external data receiving device to determine if the data packet is a valid data packet, a data packet with an error, or a null packet, and means for marking the data packet in accordance with the interrogation.
Claim 16
Dependent Claim
115 words
An intelligent DMA controller comprising: a channel for receiving and transmitting data, in the form of a data packet, to and from the DMA controller; a plurality of internal control registers used to control the transmitting of the data packet through the data channel; and a pre-parsing section configured to determine the status of a received data packet prior to the data packet being processed by a host processor, the pre-parsing section including a means for interrogating an external data receiving device to determine if the data packet is a valid data packet, a data packet with an error, or a null packet, and means for marking the data packet in accordance with the interrogation.
Claim 17
Dependent Claim
20 words
The intelligent DMA controller according to claim 13 further including a plurality of data channels which receive and send data.
Claim 18
Dependent Claim
24 words
The intelligent DMA controller according to claim 14 including a plurality of internal registers which determine the configuration of the plurality of data channels.
Claim 19
Dependent Claim
21 words
The intelligent DMA controller according to claim 13 wherein the DMA controller is configured to receive a plurality of interrupt signals.
Claim 20
Dependent Claim
35 words
The intelligent DMA controller according to claim 13 further including means for determining receipt of an interrupt signal not supported by the DMA controller, and means for sending a message indicating such lack of support.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |