US5808347A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MIS transistor with gate sidewall insulating layer
Assignee: Panasonic Holdings Corp
•
Filing: 1993-02-26
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Granted: 1998-09-15
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Expires: 2013-02-26
Abstract
Abstract A MIS transistor has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.
Inventors
- 👤 Kazumi Kurimoto
- 👤 Akira Hiroki
- 👤 Shinji Odanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/021; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
185 words
A MIS transistor, comprising: a semiconductor substrate of a first conduction type; a first insulating film and a gate electrode which are selectively formed on said semiconductor substrate; a second insulating film having a first portion formed on a side surface of said gate electrode and a second portion formed on said semiconductor substrate; a first gate side wall insulating film provided on a surface of said first portion of said second insulating film and a surface of said second portion of said second insulating film and having a dielectric constant greater than that of said second insulating film, said first gate side wall film having a height smaller than that of said gate electrode; a low density diffusion layer of a second conduction type formed on said semiconductor substrate so as to be disposed below and around said gate electrode so that each end part of said gate electrode overlaps said low density diffusion layer; and a second gate side wall insulating film which covers all surfaces of said first gate side wall film which are not in contact with said second insulating film.
Claim 2
Dependent Claim
185 words
A MIS transistor, comprising: a semiconductor substrate of a first conduction type; a first insulating film and a gate electrode which are selectively formed on said semiconductor substrate; a second insulating film having a first portion formed on a side surface of said gate electrode and a second portion formed on said semiconductor substrate; a first gate side wall insulating film provided on a surface of said first portion of said second insulating film and a surface of said second portion of said second insulating film and having a dielectric constant greater than that of said second insulating film, said first gate side wall film having a height smaller than that of said gate electrode; a low density diffusion layer of a second conduction type formed on said semiconductor substrate so as to be disposed below and around said gate electrode so that each end part of said gate electrode overlaps said low density diffusion layer; and a second gate side wall insulating film which covers all surfaces of said first gate side wall film which are not in contact with said second insulating film.
Claim 3
Dependent Claim
54 words
A MIS transistor according to claim 1, further comprising a high-density diffusion layer which is formed on said semiconductor substrate to be disposed below and around said first gate side wall insulating film and wherein said first gate side wall insulating film has an edge which reaches a position above said high-density diffusion layer.
Claim 4
Dependent Claim
23 words
A MIS transistor according to claim 2, wherein said first gate side wall insulating film is made of Ta 2 O 5 .
Claim 5
Dependent Claim
18 words
A MIS transistor according to claim 2, wherein said second gate side wall insulating film SiO 2 .
Claim 6
Dependent Claim
45 words
A MIS transistor according to claim 1, further comprising a high-density diffusion layer formed on said semiconductor substrate and one of a source electrode or a drain electrode which makes contact with said high-density diffusion layer and overlaps said second gate side wall insulating film.
Claim 7
Dependent Claim
23 words
A MIS transistor according to claim 5, wherein said first gate side wall insulating film is made of Ta 2 O 5 .
Claim 8
Dependent Claim
21 words
A MIS transistor according to claim 5, wherein said second gate side wall insulating film is made of SiO 2 .
Claim 9
Dependent Claim
29 words
A MIS transistor according to claim 1, further comprising a high-density diffusion layer formed on said semiconductor substrate so as to be disposed below and around said gate electrode.
Claim 10
Dependent Claim
23 words
A MIS transistor according to claim 8, wherein said first gate side wall insulating film is made of Ta 2 O 5 .
Claim 11
Dependent Claim
21 words
A MIS transistor according to claim 8, wherein said second gate side wall insulating film is made of SiO 2 .
Claim 12
Dependent Claim
23 words
A MIS transistor according to claim 2, wherein said first gate side wall insulating film is made of Ta 2 O 5 .
Claim 13
Dependent Claim
21 words
A MIS transistor according to claim 2, wherein said second gate side wall insulating film is made of SiO 2 .
References Cited (Backward Citations)
JPS58206160A
Cited
US4545114A
Cited
JPS60175455A
Cited
JPS6211260A
Cited
US4808543A
Cited
JPS6370458A
Cited
JPS63181378A
Cited
JPS63308963A
Cited
US4818334A
Cited
US5013675A
Cited
US4951100A
Cited
JPH0342843A
Cited
US5073514A
Cited
US4994404A
Cited
JPH0316141A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |