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US5805909A Expired / Lapsed US ⏱️ 0.0 years remaining

Microprocessors or microcontroller utilizing FLL clock having a reduced power state

Assignee: Texas Instruments Inc
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Filing: 1995-08-03
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Granted: 1998-09-08
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Expires: 2015-08-03
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Abstract

Abstract A microprocessor or micro-controller of a module design and adapted for low power is described. Each of the modules is addressed and controlled by the CPU in the same way. All assembler instructions and all address modes can be applied to each module. Also, all 16 registers of the CPU are identical in character and can be used with each of the seven address modes. One such device is available in a 4K Byte or 8K Byte ROM, EPROM or RAM version (for prototyping). The high precision 12-bit A/D converter (which can be expanded to 14 bits without additional components) is combined with an LDC drive to output measurement results; the FET driver to switch on loads; the 8-bit Timer/Counter; several I/O ports which accept interrupts; and a watchdog which guarantees safe operation during unexpected events. Up to 16 nested interrupt levels (7 used in the first product) are active during all Processor/Power modes to capture various external events or timer results. A powerful set of only 51 assembler instructions and 76 address modes allow convenient and fast programming. The CPU can be programmed with minimal effort and a small number of code lines and is extremely economical with ROM space (the number of code lines for a task is a measurement of the programming time).

Inventors

  • 👤 Horst Diewald

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 14:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814; Y; Y02; Y02D; Y02D10/00

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 95 words
A microprocessor or micro-controller formed as a single integrated circuit comprising: a plurality of similarly addressed modules at least one of said modules being an analog module or an analog interface module; a clock circuit including a Frequency Locked Loop (FLL) circuit for clocking said microprocessor or micro-controller, said FLL circuit having two states, one of said states having a frequency lock loop active and the other of said states having said frequency lock loop inactive; and a register under control of said microprocessor or micro-controller for controlling the state of said frequency lock loop.
Claim 2
Dependent Claim 95 words
A microprocessor or micro-controller formed as a single integrated circuit comprising: a plurality of similarly addressed modules at least one of said modules being an analog module or an analog interface module; a clock circuit including a Frequency Locked Loop (FLL) circuit for clocking said microprocessor or micro-controller, said FLL circuit having two states, one of said states having a frequency lock loop active and the other of said states having said frequency lock loop inactive; and a register under control of said microprocessor or micro-controller for controlling the state of said frequency lock loop.
Claim 3
Dependent Claim 20 words
A microprocessor or (*) claimed in claim 1 and wherein said analog interface module is an analog to digital converter.
Claim 4
Dependent Claim 21 words
A microprocessor or micro-controller as claimed in claim 1 and wherein said analog interface module is a digital to analog converter.
Claim 5
Dependent Claim 51 words
A microprocessor or micro-controller as claimed in claim 1 and including: a central processing unit; a program memory; a data memory; a control circuit for controlling the operating of the processor; one or more peripheral modules controlled by the CPU; and a plurality of buses connecting the components of the processor.
Claim 6
Dependent Claim 30 words
A microprocessor or micro-controller as claimed in claim 1 and wherein said state of said FLL where said loop control is inactive provides a power saving or low power mode.
Claim 7
Dependent Claim 21 words
A microprocessor or micro-controller as claimed in claim 5 and having a plurality of different power saving or low power modes.
Claim 8
Dependent Claim 15 words
A microprocessor or micro-controller as claimed in claim 6 and wherein said modes are selectable.
Claim 9
Dependent Claim 27 words
A microprocessor or micro-controller as claimed in claim 6 and wherein one of said modes provides a greater power saving or requires a lower power than another.
Claim 10
Dependent Claim 23 words
A microprocessor or micro-controller as claimed in claim 6 and wherein said mode are arranged to switch off parts of the device stepwise.
Claim 11
Dependent Claim 19 words
A microprocessor or micro-controller as claimed in claim 1 and wherein internal architecture is optimized for low power consumption.
Claim 12
Dependent Claim 74 words
In a microprocessor or micro-controller having operations controlled by a clock signal, a power saving circuit comprising: a Frequency Locked Loop (FLL) circuit generating said clock signal, said FLL circuit having two states, one of said states having a frequency lock loop ON and the other of said states having said frequency lock loop OFF; and a register for storing at least one control bit for controlling said state of said frequency lock loop.
Claim 13
Dependent Claim 74 words
In a microprocessor or micro-controller having operations controlled by a clock signal, a power saving circuit comprising: a Frequency Locked Loop (FLL) circuit generating said clock signal, said FLL circuit having two states, one of said states having a frequency lock loop ON and the other of said states having said frequency lock loop OFF; and a register for storing at least one control bit for controlling said state of said frequency lock loop.

References Cited (Backward Citations)

US4677322A Cited
US4918405A Cited
US5506790A Cited
US5422807A Cited
US5537650A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-09-07 2002-03-09 2002-09-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-09-07 2006-03-09 2006-09-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-09-07 2010-03-09 2010-09-08 $7700.00 Window Closed / Lapsed

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