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Patent US5805486A successfully refreshed from Google Patents.
US5805486A
Expired / Lapsed
US
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Moderately coupled floating point and integer units
Assignee: Intel Corp
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Filing: 1995-11-28
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Granted: 1998-09-08
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Expires: 2015-11-28
Abstract
Abstract A moderately coupled floating point and integer units of a processor allows for rapid transfer of data between the two units. The integer unit is comprised of a plurality of integer registers arranged into an integer register file and coupled to one or more integer execution units. Similarly, the floating point unit is comprised of a plurality of floating point registers arranged into a floating point register file and coupled to one or more floating point execution units. The two units operate as separate units except for the data transfer between them on a transfer bus. The transfer bus is the only direct data link between the two register files. Multiplexers are used to control the bit transfer between the two register files so that all or some of the bits of a register are transferred to a receiving register. Furthermore, the data transfer scheme allows for both numeric and Booleans to be transferred and compounding of Booleans can be performed in either numeric unit.
Inventors
- 👤 Harshvardhan Sharangpani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/3012; G06F9/3013; G06F9/30003; G06F9/30007; G06F9/30032; G06F9/38; G06F9/3877; G06F9/3879; G06F9/3881
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
240 words
A processor for performing integer and floating point calculations comprising: an integer processing unit including: an integer register file comprising a plurality of integer registers for storing integer data, each integer register having a first bit length; first read and write ports coupled to said integer register file; a floating point processing unit including: a floating point register file comprising a plurality of floating point registers for storing floating point data, each floating point register having a second bit length, said second bit length being a non-integer multiple of said first bit length, with said non-integer being greater than one; second read and write ports coupled to said floating point register file; a bus coupling said first read and write ports with said second read and write ports, said bus being dedicated to data transfer operations between said integer and floating point register files; an instruction set that includes first, second, third and fourth instructions, execution of said first and second instructions transferring a first floating point word from a first floating point register to first and second integer registers, execution of said third and fourth instructions transferring data from third and fourth integer registers to second and third floating point registers, respectively; and a switching circuit coupled between said floating point register file and said second read and write ports, said switching circuit controlling the trans-positioning of bits during data transfer between said integer and floating point register files.
Claim 2
Dependent Claim
240 words
A processor for performing integer and floating point calculations comprising: an integer processing unit including: an integer register file comprising a plurality of integer registers for storing integer data, each integer register having a first bit length; first read and write ports coupled to said integer register file; a floating point processing unit including: a floating point register file comprising a plurality of floating point registers for storing floating point data, each floating point register having a second bit length, said second bit length being a non-integer multiple of said first bit length, with said non-integer being greater than one; second read and write ports coupled to said floating point register file; a bus coupling said first read and write ports with said second read and write ports, said bus being dedicated to data transfer operations between said integer and floating point register files; an instruction set that includes first, second, third and fourth instructions, execution of said first and second instructions transferring a first floating point word from a first floating point register to first and second integer registers, execution of said third and fourth instructions transferring data from third and fourth integer registers to second and third floating point registers, respectively; and a switching circuit coupled between said floating point register file and said second read and write ports, said switching circuit controlling the trans-positioning of bits during data transfer between said integer and floating point register files.
Claim 3
Dependent Claim
12 words
The processor of claim 1 wherein said bus comprises a bi-directional bus.
Claim 4
Dependent Claim
42 words
The processor of claim 1 wherein said instruction set further comprises a fifth instruction, execution of said fifth instruction causing a logical OR operation to be performed on said second and third floating point registers, thereby producing a second floating point word.
Claim 5
Dependent Claim
50 words
The processor of claim 1 wherein execution of said first instruction transfers a mantissa value of said first floating point word to said first integer register, and execution of said second instruction transfers a sign and an exponent value of said first floating point word to said second integer register.
Claim 6
Dependent Claim
71 words
The processor of claim 1 wherein said first bit length is 64-bits and said second bit length is 80-bits, and wherein execution of said third instruction transfers bits 63:0 of said third integer register to a mantissa bit position of said second floating point register, and execution of said fourth instruction transfers bits 15:0 of said fourth integer register to sign and exponent bit positions of said third floating point register.
Claim 7
Dependent Claim
263 words
A computer system which includes a memory and a processor for performing integer and floating point calculations comprising: an integer register file coupled to said memory, said integer register file including a plurality of integer registers, each having a first bit length; an integer execution unit coupled to said integer register file which performs integer operations on data stored in said integer register file; a floating point register file coupled to said memory, said floating point register file including a plurality of floating point registers, each having a second bit length, said second bit length being a non-integer multiple of said first bit length, with said non-integer being greater than one; a floating point execution unit coupled to said floating point register file which performs floating point operations on data stored in said floating point register file; integer read/write ports coupled to said integer register file; floating point read/write ports coupled to said floating point register file; a bi-directional bus coupling said integer and floating point read/write ports, said bi-directional bus being dedicated to data transfer operations between said integer and floating point register files; an instruction set that includes first, second, third and fourth instructions, execution of said first and second transferring a first floating point word from a first floating point register to first and second integer registers, execution of said third and fourth instructions transferring data from third and fourth integer registers to second and third floating point registers, respectively; and means for trans-positioning bits during data transfer between said integer and floating point register files across said bi-directional bus.
Claim 8
Dependent Claim
263 words
A computer system which includes a memory and a processor for performing integer and floating point calculations comprising: an integer register file coupled to said memory, said integer register file including a plurality of integer registers, each having a first bit length; an integer execution unit coupled to said integer register file which performs integer operations on data stored in said integer register file; a floating point register file coupled to said memory, said floating point register file including a plurality of floating point registers, each having a second bit length, said second bit length being a non-integer multiple of said first bit length, with said non-integer being greater than one; a floating point execution unit coupled to said floating point register file which performs floating point operations on data stored in said floating point register file; integer read/write ports coupled to said integer register file; floating point read/write ports coupled to said floating point register file; a bi-directional bus coupling said integer and floating point read/write ports, said bi-directional bus being dedicated to data transfer operations between said integer and floating point register files; an instruction set that includes first, second, third and fourth instructions, execution of said first and second transferring a first floating point word from a first floating point register to first and second integer registers, execution of said third and fourth instructions transferring data from third and fourth integer registers to second and third floating point registers, respectively; and means for trans-positioning bits during data transfer between said integer and floating point register files across said bi-directional bus.
Claim 9
Dependent Claim
27 words
The computer system of claim 6 wherein said trans-positioning means comprises a switching circuit coupled between said floating point register file and said floating point read/write ports.
Claim 10
Dependent Claim
43 words
The computer system of claim 6 wherein said instruction set further comprises a fifth instruction, execution of said fifth instruction causing a logical OR operation to be performed on said second and third floating point registers, thereby producing a second floating point word.
Claim 11
Dependent Claim
51 words
The computer system of claim 6 wherein execution of said first instruction transfers a mantissa value of said first floating point word to said first integer register, and execution of said second instruction transfers a sign and an exponent value of said first floating point word to said second integer register.
Claim 12
Dependent Claim
72 words
The computer system of claim 6 wherein said first bit length is 64-bits and said second bit length is 80-bits, and wherein execution of said third instruction transfers bits 63:0 of said third integer register to a mantissa bit position of said second floating point register, and execution of said fourth instruction transfers bits 15:0 of said fourth integer register to sign and exponent bit positions of said third floating point register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |