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US5804492A
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Method of fabricating an isolation region for semiconductor device
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-06-11
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Granted: 1998-09-08
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Expires: 2017-06-11
Abstract
Abstract A method of forming an isolation region is provided. A silicon oxide layer (4) is formed on a wafer (2). A first silicon oxynitride (6) layer is formed on the silicon oxide layer, and a silicon nitride layer (8) is formed on the first silicon oxynitride layer. The silicon nitride layer and a portion of the silicon oxynitride layer are etched. A TEOS-oxide layer (10) is deposited on the first silicon oxynitride layer and on the silicon nitride layer. Sidewall spacers (12) are formed on the sidewalls of the silicon nitride layer. A second silicon oxynitride layer (14) is deposited on the silicon nitride layer, sidewall spacers, and the silicon oxide layer. A second silicon nitride layer (16) is deposited and formed on the second oxynitride layer. A sacrificial oxide layer (18) is deposited on the second silicon nitride layer. A portion of the sacrificial oxide layer is etched. The second silicon oxynitride layer and the second silicon nitride layer that are not covered by the oxide layer are removed by dry etching. The sidewall spacers are subsequently removed to create grooves (20) adjacent the first silicon nitride layer. A thermal oxidation process is performed to form isolation regions (22) adjacent the first silicon nitride layer and in the wafer, and the first silicon nitride layer, the second silicon nitride layer, and the second silicon oxynitride layer are removed.
Inventors
- 👤 Yun-Hung Shen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:55
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
247 words
A method for forming an isolation region between semiconductor devices on a semiconductor wafer, the method comprising: forming a first pad layer on the wafer as a first block layer; forming a first silicon nitride layer on said first pad layer; patterning said first silicon nitride layer to expose first portions of the said pad layer; removing said first portions of said first pad layer using said first silicon nitride layer as a mask; forming sidewall spacers on the sidewalls of said first silicon nitride layer; removing second portions of said first pad layer that are exposed by said first silicon nitride layer and said sidewall spacers; forming a second pad layer on said first silicon nitride layer, the sidewall spacers, and said exposed first pad layer for acting as a second block layer; forming a sacrificial oxide layer on said second pad oxide layer; etching the sacrificial oxide layer to expose third portions of said second pad layer; removing fourth portions of said second pad layer to expose fifth portions of said sidewall spacers using said sacrificial oxide layer as a mask; removing said sidewall spacers using said sacrificial oxide layer as a mask to form grooves between said first silicon nitride layer and said second pad layer, the grooves exposing the sixth portions of said first pad layer; forming isolation regions in said grooves and in the wafer; removing said first silicon nitride layer; and removing said first pad layer and said second pad layer.
Claim 2
Independent Claim
247 words
A method for forming an isolation region between semiconductor devices on a semiconductor wafer, the method comprising: forming a first pad layer on the wafer as a first block layer; forming a first silicon nitride layer on said first pad layer; patterning said first silicon nitride layer to expose first portions of the said pad layer; removing said first portions of said first pad layer using said first silicon nitride layer as a mask; forming sidewall spacers on the sidewalls of said first silicon nitride layer; removing second portions of said first pad layer that are exposed by said first silicon nitride layer and said sidewall spacers; forming a second pad layer on said first silicon nitride layer, the sidewall spacers, and said exposed first pad layer for acting as a second block layer; forming a sacrificial oxide layer on said second pad oxide layer; etching the sacrificial oxide layer to expose third portions of said second pad layer; removing fourth portions of said second pad layer to expose fifth portions of said sidewall spacers using said sacrificial oxide layer as a mask; removing said sidewall spacers using said sacrificial oxide layer as a mask to form grooves between said first silicon nitride layer and said second pad layer, the grooves exposing the sixth portions of said first pad layer; forming isolation regions in said grooves and in the wafer; removing said first silicon nitride layer; and removing said first pad layer and said second pad layer.
Claim 3
Dependent Claim
24 words
The method of claim 1, further comprising: performing a planarization on said wafer after removing said first pad layer and said second pad layer.
Claim 4
Dependent Claim
50 words
The method of claim 1, wherein said first pad layer comprises a first sublayer and a second sublayer, said first sublayer being formed on said wafer, said second sublayer being formed on said first sublayer, said first sublayer comprising silicon oxide and said second sublayer comprising a first silicon oxynitride.
Claim 5
Dependent Claim
20 words
The method of claim 3, wherein removing said first portions of said first pad layer stops at said first sublayer.
Claim 6
Dependent Claim
44 words
The method of claim 1, wherein said second pad layer comprises a third sublayer and a fourth sublayer, said forth sublayer being formed on said third sublayer, said third sublayer comprising a second silicon oxynitride and said fourth sublayer comprising a second silicon nitride.
Claim 7
Dependent Claim
33 words
The method of claim 1, wherein forming said sidewall spacers comprises: forming an oxide layer on said first pad layer and on said first silicon nitride layer; and anisotropically etching said oxide layer.
Claim 8
Dependent Claim
14 words
The method of claim 6, wherein said oxide layer is a tetraethyl orthosilicate-oxide layer.
Claim 9
Dependent Claim
14 words
The method of claim 6, wherein said sidewall spacers are removed by HF etching.
Claim 10
Dependent Claim
15 words
The method of claim 6, wherein said sidewall spacers are removed by buffer oxide etching.
Claim 11
Dependent Claim
12 words
The method of claim 1, wherein said sacrificial oxide layer comprises BPSG.
Claim 12
Dependent Claim
12 words
The method of claim 1, wherein said sacrificial oxide layer comprises BSG.
Claim 13
Dependent Claim
24 words
The method of claim 10, wherein the etchant for removing said sacrificial oxide layer is selected from said group consisting of BOE and HF.
Claim 14
Dependent Claim
24 words
The method of claim 11, wherein the etchant for removing said sacrificial oxide layer is selected from said group consisting of BOE and HF.
Claim 15
Dependent Claim
14 words
The method of claim 1, wherein forming said isolation regions comprises performing thermal oxidation.
References Cited (Backward Citations)
US5173444A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
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