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US5804480A
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method for forming a DRAM capacitor using HSG-Si technique and oxygen implant
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-02-28
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Granted: 1998-09-08
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Expires: 2017-02-28
Abstract
Abstract A method for forming a DRAM capacitor using a HSG-Si includes forming a dielectric layer over a substrate. A polysilicon layer is formed over the dielectric layer, and a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process. The HSG-Si layer includes a large number of silicon grains spaced apart on the surface of the polysilicon layer with the area of the polysilicon layer's surface being left exposed. Next, oxygen is implanted into the polysilicon layer using the silicon grains as an implant mask, thereby forming oxygen regions in the polysilicon layer. The HSG-Si layer is removed and the oxygen regions are annealed to transform the atom regions into oxide regions. Afterwards, the polysilicon layer is etched using the oxide regions as an etching mask, thereby forming a large number of trenches in the polysilicon layer. The oxide regions and portions of the polysilicon layer are removed to form a storage node, which serves as a bottom electrode of the DRAM cell capacitor.
Inventors
- 👤 Chih-Yuan Lu
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/32; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
318 words
A method for forming a capacitor of a dynamic random access memory cell, the method comprising: forming a dielectric layer over a substrate; forming and patterning a first photoresist layer on the dielectric layer, said first photoresist layer defining a contact area over a portion of a substrate surface; removing a portion of the dielectric layer left uncovered by the first photoresist layer to form a first trench exposing said portion of the substrate surface; forming a polysilicon layer over the dielectric layer, wherein said first trench in the dielectric layer is filled by the polysilicon layer; forming a hemispherical-grained silicon (HSG-Si) layer on the polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the polysilicon layer between said plurality of silicon grains are uncovered by the HSG-Si layer; implanting particles into said portions of the polysilicon layer not covered by said plurality of silicon grains, thereby forming a plurality of particle regions in the polysilicon layer; removing said HSG-Si layer, thereby exposing portions of the polysilicon layer that were covered by said plurality of silicon grains; annealing said plurality of particle regions, wherein said implanted particles react with said polysilicon layer to form a dielectric material, thereby transforming the plurality of particle regions into a plurality of dielectric regions; removing portions of the polysilicon layer not covered by said plurality of dielectric regions, thereby forming a plurality of second trenches in the polysilicon layer; removing said plurality of dielectric regions; forming and patterning a second photoresist layer on the polysilicon layer, said second photoresist layer defining a storage node over a portion of said polysilicon layer, said second photoresist layer covering the first trench; and removing portions of the polysilicon layer uncovered by said second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory cell.
Claim 2
Independent Claim
318 words
A method for forming a capacitor of a dynamic random access memory cell, the method comprising: forming a dielectric layer over a substrate; forming and patterning a first photoresist layer on the dielectric layer, said first photoresist layer defining a contact area over a portion of a substrate surface; removing a portion of the dielectric layer left uncovered by the first photoresist layer to form a first trench exposing said portion of the substrate surface; forming a polysilicon layer over the dielectric layer, wherein said first trench in the dielectric layer is filled by the polysilicon layer; forming a hemispherical-grained silicon (HSG-Si) layer on the polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the polysilicon layer between said plurality of silicon grains are uncovered by the HSG-Si layer; implanting particles into said portions of the polysilicon layer not covered by said plurality of silicon grains, thereby forming a plurality of particle regions in the polysilicon layer; removing said HSG-Si layer, thereby exposing portions of the polysilicon layer that were covered by said plurality of silicon grains; annealing said plurality of particle regions, wherein said implanted particles react with said polysilicon layer to form a dielectric material, thereby transforming the plurality of particle regions into a plurality of dielectric regions; removing portions of the polysilicon layer not covered by said plurality of dielectric regions, thereby forming a plurality of second trenches in the polysilicon layer; removing said plurality of dielectric regions; forming and patterning a second photoresist layer on the polysilicon layer, said second photoresist layer defining a storage node over a portion of said polysilicon layer, said second photoresist layer covering the first trench; and removing portions of the polysilicon layer uncovered by said second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory cell.
Claim 3
Dependent Claim
32 words
The method according to claim 1, wherein said substrate includes a metal-oxide-semiconductor transistor formed in and on the substrate, said metal-oxide-semiconductor transistor being a part of the dynamic random access memory cell.
Claim 4
Dependent Claim
13 words
The method according to claim 1, wherein said dielectric layer comprises silicon oxide.
Claim 5
Dependent Claim
31 words
The method according to claim 1, wherein said plurality of silicon grains each have a diameter of about 50˜500 angstroms and a spacing between adjacent silicon grains of about 100˜1000 angstroms.
Claim 6
Dependent Claim
17 words
The method according to claim 1, wherein said HSG-Si layer is removed by a chemical-mechanical polishing method.
Claim 7
Dependent Claim
25 words
The method according to claim 1, wherein the plurality of second trenches is formed by etching said polysilicon layer using a chemical dry etch method.
Claim 8
Dependent Claim
25 words
The method according to claim 1, wherein the plurality of second trenches is formed by etching said polysilicon layer using an reactive ion etch method.
Claim 9
Dependent Claim
12 words
The method according to claim 1, wherein said particles comprise oxygen atoms.
Claim 10
Dependent Claim
13 words
The method according to claim 1, wherein said polysilicon layer comprises doped polysilicon.
Claim 11
Dependent Claim
19 words
The method according to claim 1, wherein said HSG-Si layer is removed after annealing the plurality of particle regions.
Claim 12
Independent Claim
336 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming an oxide layer over a substrate; forming and patterning a first photoresist layer over the oxide layer, said first photoresist layer defining a contact area over a portion of a surface of the substrate; removing a portion of the oxide layer uncover by the first photoresist layer to form a first trench exposing said portion of the substrate surface; forming a doped polysilicon layer over the oxide layer, wherein said first trench in the oxide layer is filled by the doped polysilicon layer; forming a hemispherical-grained silicon (HSG-Si) layer on the doped polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the doped polysilicon layer between each silicon grain of the plurality of silicon grains is not covered by the HSG-Si layer; implanting oxygen particles into said portions of the doped polysilicon layer not covered by the plurality of silicon grains, thereby forming a plurality of oxygen regions in the doped polysilicon layer between silicon grains of the plurality of silicon grains; removing said HSG-Si layer, thereby exposing portions of the doped polysilicon layer that were covered by the plurality of silicon grains; annealing said plurality of oxygen regions, thereby forming a plurality of silicon oxide regions in the doped polysilicon layer; removing said portions of the doped polysilicon layer not covered by said plurality of silicon oxide regions, thereby forming a plurality of second trenches in the doped polysilicon layer; removing said plurality of silicon oxide regions; forming and patterning a second photoresist layer on the doped polysilicon layer, said second photoresist layer defining a storage node over a portion of said doped polysilicon layer, said second photoresist layer covering the first trench; and removing portions of the doped polysilicon layer not covered by the second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory cell.
Claim 13
Independent Claim
336 words
A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming an oxide layer over a substrate; forming and patterning a first photoresist layer over the oxide layer, said first photoresist layer defining a contact area over a portion of a surface of the substrate; removing a portion of the oxide layer uncover by the first photoresist layer to form a first trench exposing said portion of the substrate surface; forming a doped polysilicon layer over the oxide layer, wherein said first trench in the oxide layer is filled by the doped polysilicon layer; forming a hemispherical-grained silicon (HSG-Si) layer on the doped polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the doped polysilicon layer between each silicon grain of the plurality of silicon grains is not covered by the HSG-Si layer; implanting oxygen particles into said portions of the doped polysilicon layer not covered by the plurality of silicon grains, thereby forming a plurality of oxygen regions in the doped polysilicon layer between silicon grains of the plurality of silicon grains; removing said HSG-Si layer, thereby exposing portions of the doped polysilicon layer that were covered by the plurality of silicon grains; annealing said plurality of oxygen regions, thereby forming a plurality of silicon oxide regions in the doped polysilicon layer; removing said portions of the doped polysilicon layer not covered by said plurality of silicon oxide regions, thereby forming a plurality of second trenches in the doped polysilicon layer; removing said plurality of silicon oxide regions; forming and patterning a second photoresist layer on the doped polysilicon layer, said second photoresist layer defining a storage node over a portion of said doped polysilicon layer, said second photoresist layer covering the first trench; and removing portions of the doped polysilicon layer not covered by the second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory cell.
Claim 14
Dependent Claim
32 words
The method according to claim 11, wherein said substrate includes a metal-oxide-semiconductor transistor formed in and on the substrate, said metal-oxide-semiconductor transistor being a part of the dynamic random access memory cell.
Claim 15
Dependent Claim
35 words
The method according to claim 11, wherein said each silicon grain of the plurality of silicon grains has a diameter of about 50˜500 angstroms and a spacing between adjacent silicon grains of about 100˜1000 angstroms.
Claim 16
Dependent Claim
17 words
The method according to claim 11, wherein said HSG-Si layer is removed by a chemical-mechanical polish method.
Claim 17
Dependent Claim
26 words
The method according to claim 11, wherein the plurality of second trenches is formed by etching the doped polysilicon layer using a chemical dry etch method.
Claim 18
Dependent Claim
26 words
The method according to claim 11, wherein the plurality of second trenches is formed by etching the doped polysilicon layer using a reactive ion etch method.
Claim 19
Dependent Claim
17 words
The method according to claim 11, wherein said HSG-Si layer is removed after annealing said oxygen regions.
Claim 20
Independent Claim
223 words
A method for forming an integrated circuit capacitor, the method comprising: forming an oxide layer over a substrate; forming a doped polysilicon layer over the oxide layer; forming a hemispherical-grained silicon (HSG-Si) layer on the doped polysilicon layer, said HSG-Si layer comprising a plurality of spaced apart silicon grains, wherein portions of the doped polysilicon layer between each silicon grain of the plurality of silicon grains is not covered by the HSG-Si layer; implanting oxygen into said portions of the doped polysilicon layer not covered by the plurality of silicon grains, thereby forming a plurality of oxygen regions in the doped polysilicon layer between silicon grains of the plurality of silicon grains; removing said HSG-Si layer, thereby exposing portions of the doped polysilicon layer that were covered by the plurality of silicon grains; annealing said plurality of oxygen regions, thereby forming a plurality of oxide regions in the doped polysilicon layer; removing portions of the doped polysilicon layer not covered by said plurality of oxide regions, thereby forming a plurality of trenches in the doped polysilicon layer, wherein the plurality of trenches causes said doped polysilicon layer to have an increased surface area; removing said plurality of oxide regions; and removing portions of the doped polysilicon layer to form a doped polysilicon structure serving as a bottom electrode of the integrated circuit capacitor.
Claim 21
Independent Claim
223 words
A method for forming an integrated circuit capacitor, the method comprising: forming an oxide layer over a substrate; forming a doped polysilicon layer over the oxide layer; forming a hemispherical-grained silicon (HSG-Si) layer on the doped polysilicon layer, said HSG-Si layer comprising a plurality of spaced apart silicon grains, wherein portions of the doped polysilicon layer between each silicon grain of the plurality of silicon grains is not covered by the HSG-Si layer; implanting oxygen into said portions of the doped polysilicon layer not covered by the plurality of silicon grains, thereby forming a plurality of oxygen regions in the doped polysilicon layer between silicon grains of the plurality of silicon grains; removing said HSG-Si layer, thereby exposing portions of the doped polysilicon layer that were covered by the plurality of silicon grains; annealing said plurality of oxygen regions, thereby forming a plurality of oxide regions in the doped polysilicon layer; removing portions of the doped polysilicon layer not covered by said plurality of oxide regions, thereby forming a plurality of trenches in the doped polysilicon layer, wherein the plurality of trenches causes said doped polysilicon layer to have an increased surface area; removing said plurality of oxide regions; and removing portions of the doped polysilicon layer to form a doped polysilicon structure serving as a bottom electrode of the integrated circuit capacitor.
Claim 22
Dependent Claim
17 words
The method of claim 18 wherein the HSG-Si layer is formed using an initial phase HSG-Si process.
References Cited (Backward Citations)
US5256587A
Cited
US5302540A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |