Emulator with function for detecting illegal access to special function register

Claim 2

An emulator comprising: a CPU core board means for emulating a core section of a central processing unit of a microcomputer; a device dependent board means for emulating a peripheral device of the central processing unit; and an interface means for interfacing the CPU core board means and the device dependent board means with the microcomputer; wherein the interface means transfers necessary data including address information and comparison information, for detecting an illegal access to a special function register by an object device which is subject to emulation by at least one of said CPU board means and said device dependent board means, said interface means transferring the necessary data from the microcomputer to the CPU core board means; and wherein the CPU core board means comprises a special function register illegal access detector means for storing therein the address information of the necessary data transferred from the microcomputer, for processing the address information and comparison information to determine whether access by the object device is legal or not, and for outputting a signal indicative of the legality of the access of the object device via the interface means to the microcomputer, wherein the special function register illegal access detector means comprises: a readable and writable memory means for storing therein the address information input from the microcomputer; an input-output control means for controlling the memory means in accordance with a first and second mode signal received from the microcomputer; and a data analyzer means for responding to the address information read from the memory means to make a decision on the legality of the access by the object device to the special function register said decision being based on whether the special function register is to be readable, whether or not the special function register is to be writable, and whether the necessary data sent by the microcomputer includes a correct length of data corresponding to the special function register, and to output the decision.

Claim 3

An emulator comprising: a CPU core board means for emulating a core section of a central processing unit of a microcomputer; a device dependent board means for emulating a peripheral device of the central processing unit; and an interface means for interfacing the CPU core board means and the device dependent board means with the microcomputer; wherein the interface means transfers necessary data including address information and comparison information, for detecting an illegal access to a special function register by an object device which is subject to emulation by at least one of said CPU board means and said device dependent board means, said interface means transferring the necessary data from the microcomputer to the CPU core board means; and wherein the CPU core board means comprises a special function register illegal access detector means for storing therein the address information of the necessary data transferred from the microcomputer, for processing the address information and comparison information to determine whether access by the object device is legal or not, and for outputting a signal indicative of the legality of the access of the object device via the interface means to the microcomputer, wherein the special function register illegal access detector means comprises: a readable and writable memory means for storing therein address information input from the microcomputer; and an input-output control means receiving a first and second mode signal for responding to the necessary data input from the microcomputer to make a decision on the legality of the access by the object device to the special function register, based on a first determination as to whether the special function register is to be readable or writeable, and a second determination as to whether the necessary data sent by the microcomputer includes a correct length of data corresponding to the special function register and for generating an output address based on said first and second determinations, and wherein the special function register illegal access detector means outputs the decision from the memory means based on the output address.

Claim 4

An emulator comprising: a CPU core board means for emulating a core section of a central processing unit of a microcomputer; a device dependent board means for emulating a peripheral device of the central processing unit; and an interface means for interfacing the CPU core board means and the device dependent board means with the microcomputer; wherein the interface means transfers necessary data including address information and comparison information, for detecting an illegal access to a special function register by an object device which is subject to emulation by at least one of said CPU board means and said device dependent board means, said interface means transferring the necessary data from the microcomputer to the CPU core board means; and wherein the CPU core board means comprises a special function register illegal access detector means for storing therein the address information of the necessary data transferred from the microcomputer, for processing the address information and comparison information to determine whether access by the object device is legal or not, and for outputting a signal indicative of the legality of the access of the object device via the interface means to the microcomputer, wherein the special function register illegal access detector means comprises: a readable and writable memory means for storing therein address information input from the microcomputer; and an input-output control means receiving a first and second mode signal for responding to the necessary data input from the microcomputer to make a decision on the legality of the access by the object device to the special function register, based on a first determination as to whether the special function register is to be readable or writeable, and a second determination as to whether the necessary data sent by the microcomputer includes a correct length of data corresponding to the special function register and for generating an output address based on said first and second determinations, and wherein the special function register illegal access detector means outputs the decision from the memory means based on the output address.

Claim 5

An emulator according to claim 1, wherein said input-output control means includes: an inverter receiving said first mode signal and outputting a result to a read/write control terminal of said memory means; and an OR gate receiving an inverted first mode signal from said inverter and said second mode signal and outputting a logical sum of said OR gate to an output enable terminal of said memory means.

Claim 6

An emulator according to claim 3, wherein said address information input from the microcomputer includes, for each special function register, information indicating whether an address is read only, read write, write only and a bit length corresponding to the address.

Claim 7

An emulator according to claim 2, wherein the input output control means includes: an inverter receiving said first mode signal and outputting a result to a read/write control terminal of said memory means; an OR gate receiving an inverted first mode signal from said inverter and said second mode signal and outputting a logical sum of said OR gate to an output enable terminal of said memory means; and an AND gate receiving a first and second comparison information from said microcomputer to make the first determination as to whether the special function register is to be readable or writable and outputting a logical product of said AND gate to address control terminals of said memory means.

Claim 8

An emulator according to claim 5, wherein said address information input from the microcomputer includes a first block of addresses indicating which of said special function registers permits an 8-bit write operation; a second block of addresses indicating which is said special function registers permits an 8-bit read operation; a third block of addresses indicating which of said special function registers permits a 16-bit write operation; and a fourth block of addresses indicating which of said function registers permits a 16-bit read operation.