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US5802132A
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Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
Assignee: Intel Corp
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Filing: 1996-09-06
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Granted: 1998-09-01
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Expires: 2016-09-06
Abstract
Abstract A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
Inventors
- 👤 Chakrapani Pathikonda
- 👤 Matthew A. Fisch
- 👤 Michael W. Rhodehamel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:10
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
150 words
A processor for use in a system, said processor comprising: a clock generator to generate a core clock signal and first and second bus clock signals, wherein a ratio of each of the first or second bus clock signals to the core clock signal is 2/N where N is an odd integer greater than 2, wherein each pulse of the second bus clock signal is aligned with a distinct pulse of the core clock signal; a core coupled to the clock generator; and an interface coupled to the core and having a first and second portions operable in response to the first and second bus clock signals respectively, the first portion interfacing the processor to a system external to the processor and the second portion interfacing the core to the first portion, where information transfer between the core and the first portion occur according to the second bus clock signal.
Claim 2
Dependent Claim
150 words
A processor for use in a system, said processor comprising: a clock generator to generate a core clock signal and first and second bus clock signals, wherein a ratio of each of the first or second bus clock signals to the core clock signal is 2/N where N is an odd integer greater than 2, wherein each pulse of the second bus clock signal is aligned with a distinct pulse of the core clock signal; a core coupled to the clock generator; and an interface coupled to the core and having a first and second portions operable in response to the first and second bus clock signals respectively, the first portion interfacing the processor to a system external to the processor and the second portion interfacing the core to the first portion, where information transfer between the core and the first portion occur according to the second bus clock signal.
Claim 3
Dependent Claim
71 words
The processor defined in claim 1 wherein a high pulse occurs at the same time for the second bus clock signal and the first bus clock signal when the bus and core clock signals are in phase and occurs, for the second bus clock signal, one core clock phase earlier than the first bus clock signal when the first bus clock signal and the core clock signal are out of phase.
Claim 4
Dependent Claim
16 words
The processor defined in claim 1 wherein the first portion interface comprise a plurality of pads.
Claim 5
Dependent Claim
43 words
The processor defined in claim 1 wherein the interface comprises circuitry that interacts with the core while the core operates at N/2 times the frequency of the first and second bus clock signals and N times the frequency of operation of the circuitry.
Claim 6
Dependent Claim
16 words
A processor defined in claim 1 wherein the second portion of the interface comprises 1/N logic.
Claim 7
Dependent Claim
25 words
A processor defined in claim 1 wherein transfers through the first portion of the interface occur on one phase of the first bus clock signal.
Claim 8
Dependent Claim
14 words
A processor defined in claim 6 wherein the one phase is the high phase.
Claim 9
Dependent Claim
42 words
The processor in claim 1 wherein the clock generator further comprises: a core clock generator to generate the core clock signal; a first circuitry to generate the first bus clock signal; and a second circuitry to generate the second bus clock signal.
Claim 10
Dependent Claim
45 words
The processor in claim 8 wherein the clock generator further comprises a bus clock enable generation logic to generate first and second bus clock enable indications, wherein the first circuitry generates the first bus clock signal using the first and second bus clock enable indications.
Claim 11
Dependent Claim
17 words
The processor in claim 9 wherein the first and second bus clock enable indications comprise enable signals.
Claim 12
Dependent Claim
66 words
The processor in claim 9 wherein the first circuitry selects clock pulses of the core clock signal to create the first bus clock signal, wherein the first circuitry selects clock pulses that are in phase with the core clock signal using the first bus enable indication and selects clock pulses which are out of phase with the core clock signal using the second bus enable indication.
Claim 13
Dependent Claim
26 words
The processor in claim 9 wherein the second circuitry generates a second bus clock signal by shifting the second bus clock enable indication by one phase.
Claim 14
Dependent Claim
45 words
The processor in claim 9 wherein the first circuitry generates the first bus clock signal by selecting every N/2 cycles of the core clock signal in response to the first and second bus clock enable indications where N is an odd integer greater than two.
Claim 15
Dependent Claim
70 words
The processor in claim 1 wherein the clock generator further comprises: a detector to determine whether the core clock signal is out of phase with the first bus clock signal; and correction circuitry coupled to the detector to place the core clock signal in phase with the first bus clock signal if the detector determines that the core clock signal is out of phase with the first bus clock signal.
Claim 16
Dependent Claim
140 words
A processor for use in a system, said processor comprising: means for generating a core clock signal and first and second bus clock signals, wherein a ratio of both the first and second bus clock signals to the core clock signal is 2/N where N is an odd integer greater than 2; processing means for processing information in response to the core clock signal; and interface means for interfacing the means for processing to an external system, the interface means having a first and second means operable in response to the first and second bus clock signals, respectively, the first means for interfacing the processor to the external system and the second means for interfacing the processing means to the first means, where information transfer between the processing means and first means occurs according to the second bus clock signal.
Claim 17
Dependent Claim
140 words
A processor for use in a system, said processor comprising: means for generating a core clock signal and first and second bus clock signals, wherein a ratio of both the first and second bus clock signals to the core clock signal is 2/N where N is an odd integer greater than 2; processing means for processing information in response to the core clock signal; and interface means for interfacing the means for processing to an external system, the interface means having a first and second means operable in response to the first and second bus clock signals, respectively, the first means for interfacing the processor to the external system and the second means for interfacing the processing means to the first means, where information transfer between the processing means and first means occurs according to the second bus clock signal.
Claim 18
Dependent Claim
70 words
The processor defined in claim 15 wherein a high pulse occurs at the same time for the second bus clock and the first bus clock signal when the bus and core clock signals are in phase and occurs, for the second bus clock signal, one core clock phase earlier than the first bus clock signal when the first bus clock signal and the core clock signal are out of phase.
Claim 19
Dependent Claim
17 words
The processor defined in claim 15 wherein the first portion of interface comprise a plurality of pads.
Claim 20
Dependent Claim
46 words
The processor defined in claim 15 wherein the interface means comprises circuitry that interacts with the processing means while the processing means operates at N/2 times the frequency of the first and second bus clock signals and N times the frequency of operation of the circuitry.
Claim 21
Dependent Claim
71 words
A processor comprising: a clock generator to generate a core clock signal and a first bus clock signal, wherein a ratio of the first bus clock signal to the core clock signal is 2/N and further wherein the clock generator generates the first bus clock signal by alternating the first bus clock signal between two 1/N ratios with respect to the core clock signal; a core coupled to the clock generator.
Claim 22
Dependent Claim
71 words
A processor comprising: a clock generator to generate a core clock signal and a first bus clock signal, wherein a ratio of the first bus clock signal to the core clock signal is 2/N and further wherein the clock generator generates the first bus clock signal by alternating the first bus clock signal between two 1/N ratios with respect to the core clock signal; a core coupled to the clock generator.
Claim 23
Dependent Claim
17 words
The processor defined in claim 19 wherein the two 1/N modes are for consecutive values of N.
Claim 24
Dependent Claim
39 words
The processor defined in claim 20 where the two 1/N modes comprises 1/2 and 1/3 modes, such that the first bus clock signal switches between 1/2 mode to 1/3 mode in alternate cycles of the first bus clock signal.
Claim 25
Dependent Claim
30 words
The processor defined in claim 19 wherein the clock generator is configured to generate a second bus clock signal being at a 2/N frequency ratio to the core clock signal.
References Cited (Backward Citations)
US5267273A
Cited
US5335253A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |