Method and apparatus for removing timing hazards in a circuit design

Claim 3

The apparatus as set forth in claim 1, wherein the apparatus is enabled by the program to automatically transform said certain storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

Claim 4

The apparatus as set forth in claim 2, wherein the apparatus is enabled by the program to determine the appropriate transformation for one of said storage circuit elements controlled by a gated synchronization signal, using the boolean function corresponding to the gating combinatorial logic, and factoring into consideration whether the pre-transformation storage circuit element has an enable control signal or not.

Claim 5

The apparatus as set forth in claim 2, wherein the apparatus is also enabled by the program to insert an AND gate into the circuit design to qualify a complementary enable signal, if employed and the pre-transformation storage circuit element has an enable control signal.

Claim 6

The apparatus as set forth in claim 1, wherein the apparatus is enabled by the program to construct each of the boolean functions using a reduced order binary decision diagram.

Claim 9

The apparatus as set forth in claim 6, wherein the apparatus is enabled by the program to insert a replicate of the division combinatorial logic of the divided synchronous signal of a storage circuit element into the circuit design to generate a predictive version of the divided synchronous signal.

Claim 10

The apparatus as set forth in claim 7, wherein the apparatus is also enabled by the program to insert a first AND gate in the circuit design to generate a logical AND of an inverted version of the divided synchronous signal and the predictive version of the divided synchronous signal.

Claim 11

The apparatus as set forth in claim 8, wherein the apparatus is also enabled by the program to provide the output of the first AND gate as the complementary enable control signal if the storage circuit element does not have an enable signal.

Claim 12

The apparatus as set forth in claim 8, wherein the apparatus is also enabled by the program to insert a second AND gate in the circuit design to qualify the output of the first AND gate by an enable signal of the storage circuit element, and then providing the qualified output as the complementary enable control signal, if the storage circuit element has such an enable signal.

Claim 13

The apparatus as set forth in claim 7, wherein the apparatus is also enabled by the program to insert for each outputting flip-flop providing input to the division combinatorial logic and having an enable signal, a multiplexor to provide a selected one of a current state or a next state of the outputting flip-flop's output to the replicated division combinatorial logic as input, the multiplexor being controlled by the enable signal of the outputting flip-flop.

Claim 14

A computer system comprising: an execution unit for executing programs; a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing, the program enables the computer system to identify certain storage circuit elements in a circuit design, said certain storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of these synchronization signals' potential skews with respect to a reference signal of the circuit design not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal; the program further enables the computer system to automatically transform said certain storage circuit elements to be controlled by synchronization signals that do not have potential skews with respect to the reference signal not being ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformation for each of said certain storage circuit elements employing a boolean function corresponding to the gating combinatorial logic, and determining at least a first and a second co-factor value of a logical decomposition of the synchronization signal using the corresponding boolean function.

Claim 15

A computer system comprising: an execution unit for executing programs; a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing, the program enables the computer system to identify certain storage circuit elements in a circuit design, said certain storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of these synchronization signals' potential skews with respect to a reference signal of the circuit design not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal; the program further enables the computer system to automatically transform said certain storage circuit elements to be controlled by synchronization signals that do not have potential skews with respect to the reference signal not being ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformation for each of said certain storage circuit elements employing a boolean function corresponding to the gating combinatorial logic, and determining at least a first and a second co-factor value of a logical decomposition of the synchronization signal using the corresponding boolean function.

Claim 16

The computer system as set forth in claim 12, wherein the computer system is enabled by the program to automatically transform the storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

Claim 19

A hardware emulation system comprising: a host system having an execution unit for executing programs, and a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing, the program enables the host system to map a circuit design onto logic and interconnect elements of the hardware emulation, including identification of certain storage circuit elements in the circuit design, said certain storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of these synchronization signals' potential skews with respect to a reference signal of the circuit design not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal, the program further enables the host system to automatically transform said certain storage circuit elements to be controlled by synchronization signals that do not have potential skews with respect to the reference signal not being ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformation for each of said certain storage circuit elements employing a boolean function corresponding to the gating combinatorial logic, and determining at least a first and a second co-factor value of a logical decomposition of the synchronization signal using the corresponding boolean function; and said logic and interconnect elements for emulating said circuit design.

Claim 20

A hardware emulation system comprising: a host system having an execution unit for executing programs, and a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing, the program enables the host system to map a circuit design onto logic and interconnect elements of the hardware emulation, including identification of certain storage circuit elements in the circuit design, said certain storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of these synchronization signals' potential skews with respect to a reference signal of the circuit design not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal, the program further enables the host system to automatically transform said certain storage circuit elements to be controlled by synchronization signals that do not have potential skews with respect to the reference signal not being ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformation for each of said certain storage circuit elements employing a boolean function corresponding to the gating combinatorial logic, and determining at least a first and a second co-factor value of a logical decomposition of the synchronization signal using the corresponding boolean function; and said logic and interconnect elements for emulating said circuit design.

Claim 21

The hardware emulation system as set forth in claim 15, wherein the host system is enabled by the program to automatically transform the storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

Claim 22

A hardware emulation system comprising: a host system having an execution unit for executing programs, and a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing, the program enables the host system to map a circuit design onto logic and interconnect elements of the hardware emulation, including identification of certain storage circuit elements in the circuit design, said certain storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of these synchronization signals' potential skews with respect to a reference signal of the circuit design not being ensured to be within a design tolerance limit, the synchronization signals being generated by division combinatorial logic based on at least the reference signal, the program further enables the host system to automatically transform said certain storage circuit elements to be controlled by synchronization signals that do not have potential skews with respect to the reference signal not being ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused; and said logic and interconnect elements for emulating said circuit design.

Claim 23

A hardware emulation system comprising: a host system having an execution unit for executing programs, and a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing, the program enables the host system to map a circuit design onto logic and interconnect elements of the hardware emulation, including identification of certain storage circuit elements in the circuit design, said certain storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of these synchronization signals' potential skews with respect to a reference signal of the circuit design not being ensured to be within a design tolerance limit, the synchronization signals being generated by division combinatorial logic based on at least the reference signal, the program further enables the host system to automatically transform said certain storage circuit elements to be controlled by synchronization signals that do not have potential skews with respect to the reference signal not being ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused; and said logic and interconnect elements for emulating said circuit design.

Claim 24

An automated method for removing timing hazards from a circuit design; said method comprising the steps of: a) identifying storage circuit elements controlled by synchronization signals that are generated by gating combinatorial logic based on at least a reference signal of the circuit design; b) determining boolean functions corresponding to the gating combnatorial logic, and determining a first and a second cofactor value of a logical decomposition of each of the gated synchronization signal using the corresponding boolean function; and c) automatically transforming each of said storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate, based at least in part on the first and the second co-factor values determined.

Claim 25

An automated method for removing timing hazards from a circuit design; said method comprising the steps of: a) identifying storage circuit elements controlled by synchronization signals that are generated by gating combinatorial logic based on at least a reference signal of the circuit design; b) determining boolean functions corresponding to the gating combnatorial logic, and determining a first and a second cofactor value of a logical decomposition of each of the gated synchronization signal using the corresponding boolean function; and c) automatically transforming each of said storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate, based at least in part on the first and the second co-factor values determined.

Claim 26

The method as set forth in claim 18, wherein said step (c) includes factoring into consideration whether a pre-transformation storage circuit element has an enable control signal or not.

Claim 27

The method as set forth in claim 18, wherein step (b) includes constructing each of the boolean functions using a reduced order binary decision diagram.

Claim 28

The method as set forth in claim 18, wherein step (c) includes inserting an AND gate into the circuit design to qualify the complementary enable signal, if employed and a pre-transformation storage circuit element has an enable control signal.

Claim 29

An automated method for removing timing hazards from a circuit design, said method comprising the steps of: (a) identifying a storage circuit element controlled by a synchronization signal that is generated by division combinatorial logic based on at least a reference signal of the circuit design; (b) inserting a replicate of the division combinatorial logic of the divided synchronous signal into the circuit design to generate a predictive version of the divided synchronous signal; and (c) automatically transforming said storage circuit element controlled by the divided synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

Claim 30

An automated method for removing timing hazards from a circuit design, said method comprising the steps of: (a) identifying a storage circuit element controlled by a synchronization signal that is generated by division combinatorial logic based on at least a reference signal of the circuit design; (b) inserting a replicate of the division combinatorial logic of the divided synchronous signal into the circuit design to generate a predictive version of the divided synchronous signal; and (c) automatically transforming said storage circuit element controlled by the divided synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

Claim 31

The method as set forth in claim 22, wherein step (c) further includes inserting a first AND gate in the circuit design to generate a logical AND of an inverted version of the divided synchronous signal and the predictive version of the divided synchronous signal.

Claim 32

The method as set forth in claim 23, wherein the step (c) further includes providing the output of the first AND gate as the complementary enable control signal if the storage circuit element does not have an enable signal.

Claim 33

The method as set forth in claim 23, wherein step (c) further includes inserting a second AND gate in the circuit design to qualify the output of the first AND gate by an enable signal of the storage circuit element, and then providing the qualified output as the complementary enable control signal, if the storage circuit element has such an enable signal.

Claim 34

The method as set forth in claim 22, wherein step (c) further includes inserting for each outputting flip-flop providing input to the division combinatorial logic and having an enable signal, a multiplexor to provide a selected one of a current state or a next state of the outputting flip-flop's output to the replicated division combinatorial logic as input, the multiplexor being controlled by the enable signal of the outputting flip-flop.