Patent US5801711A successfully refreshed from Google Patents.
US5801711A
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Polyline and triangle strip data management techniques for enhancing performance of computer graphics system
Assignee: Hewlett Packard Development Co LP
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Filing: 1995-08-08
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Granted: 1998-09-01
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Expires: 2015-08-08
Abstract
Abstract A geometry accelerator for a computer graphics system performs transformations on vertex data representative of graphics primitives, decomposes quadrilaterals into triangles, and performs lighting, clipping and plane equation calculations for each primitive. The geometry accelerator incorporates a memory mapping technique that achieves high efficiency transfer of vertex information from the host computer to the geometry accelerator. A double buffered vertex RAM with granularity permits the quantity of data transferred to the geometry accelerator to be reduced. The transformation and decomposition engines of the geometry accelerator employ data management techniques in which calculations for shared vertices and shared edges of primitives are performed only once.
Inventors
- 👤 Louise A. Koss
- 👤 Alan S. Krech, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:02
CPC Classifications
G; G06; G06T; G06T15/00; G06T15/005
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
228 words
In a computer graphics system, apparatus for processing vertex data representative of graphics primitives, comprising: a vertex RAM for storage of said vertex data; means for writing vertex data representative of first and second primitives having at least one shared vertex in said vertex RAM; a primitive RAM for storage of output data, said primitive RAM including a first buffer and a second buffer; and a processing circuit for generating said output data in response to said vertex data, said processing circuit comprising: a register file, means for processing the vertex data representative of said first primitive to provide first primitive output data, means for storing said first primitive output data in the first buffer of said primitive RAM; means for storing a portion of said first primitive output data corresponding to said shared vertex in said register file, means for processing new vertex data representative of said second primitive to provide second primitive output data, mean for storing said second primitive output data in the second buffer of said primitive RAM, and means for copying the portion of said first primitive output data corresponding to said shared vertex from said register file to the second buffer of said primitive RAM when said new vertex data is being processed, whereby the vertex data corresponding to said shared vertex is processed only once for said first and second primitives.
Claim 2
Dependent Claim
228 words
In a computer graphics system, apparatus for processing vertex data representative of graphics primitives, comprising: a vertex RAM for storage of said vertex data; means for writing vertex data representative of first and second primitives having at least one shared vertex in said vertex RAM; a primitive RAM for storage of output data, said primitive RAM including a first buffer and a second buffer; and a processing circuit for generating said output data in response to said vertex data, said processing circuit comprising: a register file, means for processing the vertex data representative of said first primitive to provide first primitive output data, means for storing said first primitive output data in the first buffer of said primitive RAM; means for storing a portion of said first primitive output data corresponding to said shared vertex in said register file, means for processing new vertex data representative of said second primitive to provide second primitive output data, mean for storing said second primitive output data in the second buffer of said primitive RAM, and means for copying the portion of said first primitive output data corresponding to said shared vertex from said register file to the second buffer of said primitive RAM when said new vertex data is being processed, whereby the vertex data corresponding to said shared vertex is processed only once for said first and second primitives.
Claim 3
Dependent Claim
83 words
Apparatus for processing vertex data as defined in claim 1 wherein said first and second primitives are first and second line segments of a polyline, said line segments having a shared vertex, and wherein said means for copying comprises means for copying the first primitive output data corresponding to the shared vertex of said first and second line segments from said register file to locations in the second buffer of said primitive RAM corresponding to a first vertex of the second line segment.
Claim 4
Dependent Claim
115 words
Apparatus for processing vertex data as defined in claim 1 wherein said first and second primitives comprise first and second triangles of a triangle strip, said triangles having two shared vertices, wherein said means for storing a portion of said first primitive output data includes means for storing output data corresponding to said two shared vertices of said first and second triangles in said register file and wherein said means for copying includes means for copying the output data corresponding to said two shared vertices of said first and second triangles from said register file to locations in the second buffer of said primitive RAM corresponding to first and second vertices of the second triangle.
Claim 5
Dependent Claim
78 words
Apparatus for processing vertex data as defined in claim 1 wherein said processing circuit further comprises means for storing unprocessed vertex data corresponding to said shared vertex in said register file and means for copying said unprocessed vertex data from said register file to the second buffer of said primitive RAM when said new vertex data is being processed, whereby the second buffer of said primitive RAM contains a complete set of vertex data for the shared vertex.
Claim 6
Dependent Claim
69 words
Apparatus for processing vertex data as defined in claim 1 wherein said vertex RAM includes a first buffer and a second buffer and said apparatus further comprises double buffering circuitry for controlling simultaneous writing of said vertex data in one of said first and second buffers of said vertex RAM and reading of said vertex data from the other of said first and second buffers of said vertex RAM.
Claim 7
Dependent Claim
27 words
Apparatus for processing vertex data as defined in claim 1 wherein said processing circuit comprises a transformation circuit for multiplying said vertex data by a transform matrix.
Claim 8
Dependent Claim
31 words
Apparatus for processing vertex data as defined in claim 1 wherein said processing circuit comprises a circuit for calculating slopes of parameters representative of said primitives between vertices of said primitives.
Claim 9
Dependent Claim
212 words
In a computer graphics system comprising a vertex RAM for storage of vertex data, a primitive RAM for storage of output data and a processing circuit for generating said output data in response to said vertex data, a method for processing vertex data representative of graphics primitives, comprising steps of: writing vertex data representative of first and second primitives having at least one shared vertex in said vertex RAM; reading the first primitive vertex data from said vertex RAM and processing the first primitive vertex data to provide first primitive output data; storing said first primitive output data in a first buffer of said primitive RAM; storing a portion of said first primitive output data corresponding to said shared vertex in a register file; reading new vertex data from said vertex RAM and processing said new vertex data to provide second primitive output data; storing said second primitive output data in a second buffer of said primitive RAM; and copying the portion of said first primitive output data corresponding to said shared vertex from said register file to the second buffer of said primitive RAM when said new vertex data is being processed, whereby the vertex data corresponding to said shared vertex is processed only once for said first and second primitives.
Claim 10
Dependent Claim
212 words
In a computer graphics system comprising a vertex RAM for storage of vertex data, a primitive RAM for storage of output data and a processing circuit for generating said output data in response to said vertex data, a method for processing vertex data representative of graphics primitives, comprising steps of: writing vertex data representative of first and second primitives having at least one shared vertex in said vertex RAM; reading the first primitive vertex data from said vertex RAM and processing the first primitive vertex data to provide first primitive output data; storing said first primitive output data in a first buffer of said primitive RAM; storing a portion of said first primitive output data corresponding to said shared vertex in a register file; reading new vertex data from said vertex RAM and processing said new vertex data to provide second primitive output data; storing said second primitive output data in a second buffer of said primitive RAM; and copying the portion of said first primitive output data corresponding to said shared vertex from said register file to the second buffer of said primitive RAM when said new vertex data is being processed, whereby the vertex data corresponding to said shared vertex is processed only once for said first and second primitives.
Claim 11
Dependent Claim
82 words
A method for processing vertex data as defined in claim 8 wherein said first and second primitives are first and second line segments of a polyline, said line segments having a shared vertex, and wherein the step of copying includes copying the first primitive output data corresponding to the shared vertex of said first and second line segments from said register file to locations in the second buffer of said primitive RAM corresponding to a first vertex of the second line segment.
Claim 12
Dependent Claim
112 words
A method for processing vertex data as defined in claim 8 wherein said first and second primitives comprise first and second triangles of a triangle strip, said triangles having two shared vertices, wherein the step of storing a portion of said first primitive output data includes storing output data corresponding to said two shared vertices of said first and second triangles in said register file and wherein the step of copying includes copying the output data corresponding to said two shared vertices of said first and second triangles from said register file to locations in the second buffer of said primitive RAM corresponding to first and second vertices of the second triangle.
Claim 13
Dependent Claim
74 words
A method for processing vertex data as defined in claim 8 further comprising the steps of storing unprocessed vertex data corresponding to said shared vertex in said register file and copying said unprocessed vertex data from said register file to the second buffer of said primitive RAM when said new vertex data is being processed, whereby the second buffer of said primitive RAM contains a complete set of vertex data for the shared vertex.
Claim 14
Dependent Claim
66 words
A method for processing vertex data as defined in claim 8 wherein said vertex RAM includes a first buffer and a second buffer and said method further comprises controlling simultaneous writing of said vertex data in one of said first and second buffers of said vertex RAM and reading of said vertex data from the other of said first and second buffers of said vertex RAM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |